中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

92 records (took 0.029 seconds)

    Nonvolatile memory device with double hierarchical decoding
    11.
    发明公开
    Nonvolatile memory device with double hierarchical decoding 审中-公开
    NichtflüchtigeSpeicheranordnung mit doppelter等级分类器Dekodierung

    公开(公告)号：EP1047077A1

    公开(公告)日：2000-10-25

    申请号：EP99830236.8

    申请日：1999-04-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Commodaro, Stefano ,  Farina, Francesco

    IPC: G11C8/00 ,  G11C16/06 ,  G11C7/18

    CPC classification number: G11C16/08 ,  G11C5/025 ,  G11C7/18 ,  G11C8/10

    Abstract: The memory array (30) comprises a plurality of cells (50), grouped together in sectors (31) and arranged in sector rows and columns, and has both hierarchical row decoding and hierarchical column decoding. Global word lines (35) are connected to at least two word lines (36) in each sector (31), through local row decoders (33); global bit lines (42) are connected to at least two local bit lines (43) in each sector (31), through local column decoders (40). The global column decoder (41) is arranged in the centre of the memory array (30), and separates from each other an upper half (30a) and a lower half (30b) of the memory array (30). Sense amplifiers (47) are also arranged in the middle of the array, thus saving space. This architecture also provides lesser stress of the cells, better reliability, and better production performance. In addition, each sector (31) is completely disconnected from the remaining sectors, and only the faulty row or column of a single sector should be doubled.

    Abstract translation: 闪存EEPROM存储器阵列（30）包括在扇区（31）中分组在一起的单元，并且具有分级行和分层列解码。 全局字线（35）通过本地行解码器（33）连接到每个扇区中的字线（36）。 全局位线（42）通过本地列解码器（40）连接到本地位线（43）。 全局列解码器（41）和读出放大器（47）将上半部分（30a）与存储器阵列的下半部分（30b）分开。

    Improved boosting circuit, particularly for a memory device
    13.
    发明公开
    Improved boosting circuit, particularly for a memory device 失效
    VerbesserteSpannungserhöhungsschaltungfürSpeicheranordnungen

    公开(公告)号：EP0915478A1

    公开(公告)日：1999-05-12

    申请号：EP97830572.0

    申请日：1997-11-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ferrario, Donato ,  Golla, Carla Maria

    IPC: G11C16/00 ,  G11C8/00 ,  G11C5/14

    CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10

    Abstract: A boosting circuit supplied by a first voltage level (Vcc) and a second voltage level (Gnd), and having an output line (13) capable of taking a third voltage level, characterized by comprising at least two distinct circuits (A1,11,A2,12) for generating said third voltage level, the at least two circuits selectively activatable for generating said third voltage level and selectively couplable to said output line (13).

    Abstract translation: 由第一电压电平（Vcc）和第二电压电平（Gnd）提供的升压电路，并且具有能够获取第三电压电平的输出线（13），其特征在于包括至少两个不同的电路（A1,11， A2,12），用于产生所述第三电压电平，所述至少两个电路选择性地激活以产生所述第三电压电平并且可选择性地耦合到所述输出线（13）。

    A memory device with row selector comprising series connected medium voltage transistors
    15.
    发明公开
    A memory device with row selector comprising series connected medium voltage transistors 有权
    在意大利语中的Speichervorrichtung mit einem Zeilenselektor mit Mantelspannungstransistoren

    公开(公告)号：EP1892724A1

    公开(公告)日：2008-02-27

    申请号：EP06119440.3

    申请日：2006-08-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C16/08 ,  G11C8/08

    CPC classification number: G11C16/08

    Abstract: A non-volatile memory device is provided. The memory device includes a memory matrix (105; 605) comprising a plurality of memory cells (Mc), arranged according to a plurality of rows and a plurality of columns. The memory device further includes a plurality of word lines (WL(i)); each word line is associated with one respective row of said plurality and is connected to the memory cells of the row; the word lines are grouped into at least one packet (WLP). The memory device includes a row selector (160; 660) coupled to the word lines and adapted to selectively biasing them. The row selector includes, for each packet of word lines, a plurality of first paths, wherein each first path is adapted to apply a first biasing voltage to a corresponding word line of the packet depending on an operation to be performed on the memory cells connected to the corresponding word line. Each first path includes at least a first (N(i)) and a second (P(i)) selection transistors series-connected between a first terminal and a second terminal of the first path. The second terminal is coupled to the corresponding word line. The memory device further includes enabling means (110) for commonly providing an enabling voltage to the first terminal of the first paths associated to a selected packet of word lines including a selected word line. The enabling voltage depends on the operation to be performed on the memory cells connected to the selected word line and is adapted to enable the execution of said operation. The memory device further includes selection means (150) for selecting one among said plurality of first paths. the selected first path corresponding to the selected word line. The selection means are adapted to activate the first selection transistor of the selected first path in order to obtain the first biasing voltage from the enabling voltage by a voltage drop introduced by the first selection transistor; said selection means are further adapted to activate the second selection transistor of the selected first path in order to transfer the first biasing voltage provided by the first selection transistor onto the selected word line.

    Abstract translation: 提供非易失性存储器件。 存储器件包括存储器矩阵（105; 605），其包括根据多行和多列布置的多个存储器单元（Mc）。 存储装置还包括多个字线（WL（i））; 每个字线与所述多个的一个相应行相关联，并连接到该行的存储单元; 字线被分组成至少一个分组（WLP）。 存储器件包括耦合到字线并适于选择性地偏置它们的行选择器（160; 660）。 行选择器对于每个字线分组包括多个第一路径，其中每个第一路径适于根据要连接的存储器单元执行的操作将第一偏置电压施加到分组的对应字线 到相应的字线。 每个第一路径包括串联连接在第一路径的第一终端和第二终端之间的至少第一（N（i））和第二（P（i））选择晶体管。 第二终端耦合到对应的字线。 存储器件还包括用于共同地向包括所选择的字线的所选择的字线分组的第一路径的第一终端提供使能电压的启用装置（110）。 使能电压取决于对连接到所选字线的存储器单元执行的操作，并且适于使得能够执行所述操作。 存储装置还包括用于选择所述多个第一路径之一的选择装置（150）。 所选择的第一路径对应于所选择的字线。 选择装置适于激活所选择的第一路径的第一选择晶体管，以便通过由第一选择晶体管引入的电压降从使能电压获得第一偏置电压; 所述选择装置还适于激活所选择的第一路径的第二选择晶体管，以便将由第一选择晶体管提供的第一偏置电压传送到所选择的字线上。

    Improvements to the design of voltage switches
    16.
    发明公开
    Improvements to the design of voltage switches 有权
    Verbesserungen am Entwurf von Spannungsschalter

    公开(公告)号：EP1837993A1

    公开(公告)日：2007-09-26

    申请号：EP06111477.3

    申请日：2006-03-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: H03K17/10 ,  G11C16/12 ,  H01L27/02

    CPC classification number: A61K31/737 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  H01L27/0266 ,  H03K17/005 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/675

    Abstract: A circuit is disclosed. The circuit comprises a first input terminal (INA1), a second input terminal (INA2) and an output terminal (OUT). The circuit further includes a first circuital branch (610) connected between the first input terminal and the output terminal, and a second circuital branch (620) connected between the second input terminal and the output terminal. The first circuital branch is selectively activatable for coupling the first input terminal with the output terminal, and the second circuital branch is selectively activatable for coupling the second input terminal with the output terminal. The first and second circuital branches comprise each at least one electronic device having at least a first and a second device terminals. Said at least one electronic device is designed to guarantee the capability of sustaining voltage differences across at least the first and second device terminals thereof that are up-limited in absolute value by a first predetermined maximum value lower than the maximum of absolute values of voltage differences between the output terminal and the first input terminal, and between the output terminal and the second input terminal, respectively.

    Abstract translation: 公开了一种电路。 该电路包括第一输入端（INA1），第二输入端（INA2）和输出端（OUT）。 电路还包括连接在第一输入端和输出端之间的第一电路分支（610）和连接在第二输入端和输出端之间的第二电路分支（620）。 第一电路分支可选择性地激活用于将第一输入端子与输出端子耦合，并且第二电路支路选择性地激活以将第二输入端子与输出端子耦合。 第一和第二电路分支包括每个至少一个具有至少第一和第二设备端子的电子设备。 所述至少一个电子设备被设计成保证在至少其第一和第二设备端子之间保持电压差的能力，所述第一和第二设备端子的绝对值上限受到低于电压差绝对值的最大值的第一预定最大值的限制 在输出端子和第一输入端子之间以及输出端子和第二输入端子之间。

    Method for replacing failed non-volatile memory cells and corresponding memory device
    19.
    发明公开
    Method for replacing failed non-volatile memory cells and corresponding memory device 有权
    一种用于替换失效非易失性存储单元和相应的存储器阵列的方法

    公开(公告)号：EP1403879A1

    公开(公告)日：2004-03-31

    申请号：EP02425591.1

    申请日：2002-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C29/00 ,  G11C16/16

    CPC classification number: G11C29/82 ,  G11C16/04 ,  G11C16/16 ,  G11C29/44 ,  G11C2029/1208

    Abstract: The invention relates to a method for replacing failed non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array (4) organized in a row-and-column layout, and divided in array sectors (20), including at least one row decode circuit portion being supplied positive and negative voltages (Vpcx,HVNEG).
    The method is applied whenever the result of the erase algorithm is negative, and comprises the following steps:-

    forcing an incompletely erased sector (20) into a read condition;
    scanning the rows of said sector (20) to check for the possible presence of a spurious current indicating a fail state;
    identifying and electrically isolating the failed row;
    re-addressing from said failed row to a redundant row provided in the same sector (20);
    re-starting the erase algorithm.

    Abstract translation: 该方法包括迫使完全擦除扇区负进一个阅读条件，只要擦除算法的问题是不完整的或。 该部门的行进行扫描，以检查虚假电流指示了失效的可能存在。 失败的行识别和电气隔离。 该失效行重新给在同一个部门重新启动算法提供一个冗余行。 因此独立claimsoft被包括为综合的非易失性存储器设备。

Patent Agency Ranking