公开(公告)号：EP1032029A1

公开(公告)日：2000-08-30

申请号：EP99830101.4

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： Cereda, Manlio Sergio ,  Brambilla, Claudio ,  Caprara, Paolo

IPC: H01L21/336 ,  H01L21/8247 ,  H01L21/033

CPC classification number: H01L27/11521 ,  H01L21/0337 ,  H01L29/66825

Abstract: A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells (1), the matrix being formed on a semiconductor substrate (2) with a plurality of continuous bit lines (BL) extending across the substrate (2) as discrete parallel strips, comprising at least the following steps:

growing an oxide layer (3) over the matrix region;
depositing the semiconductor throughout with a stack structure which comprises a first conductor layer (4), first dielectric layer (5), and second conductor layer (6):
depositing a second dielectric layer (7);
defining floating gate regions (10) by photolithography using a mask of "POLY1 along a first direction", to thereby define, in said dielectric layer (7), a plurality of parallel strips (8) which delimit a first dimension of floating gate regions;
etching away said dielectric layer (7) to define said plurality of parallel dielectric strips (8);
photolithographing by means of a mask of "POLY1 along a second direction" to define a plurality of dielectric islands (9) in said plurality of parallel strips (8);
etching away said dielectric layer (7) to define the plurality of islands (9);
etching away said stack structure (4,5,6) and the thin gate oxide layer (3) to define gate regions (10) of the matrix cells using said oxide island (9).

Abstract translation: 一种用于制造具有一虚拟接地电子半导体集成电路存储器设备和包括至少浮动栅极存储器单元（1）的矩阵处理，该矩阵被连续位线的延伸的多个（BL）形成在半导体衬底（2） 横跨基片（2）作为离散的平行条带，其包括至少以下步骤：氧化物层上生长（3）在所述基体区; 具有堆叠结构，其包括第一导体层（4），第一电介质层（5）和第二导体层沉积在整个半导体（6）上沉积第二电介质层（7）; 使用的掩模“POLY1沿着第一方向”，以由此限定，在所述电介质层（7），一个平行的条带的多元性 - 定义浮置栅极区域（10）通过光刻法（8），该界定浮栅区的第一尺寸 ; 蚀刻掉介电层。所述（7）来定义平行介质带的所述多个（8）; photolithographing通过的“POLY 1沿一第二方向”的掩模手段，以限定电介质岛的多个（9）平行条带（8）在所述多个; 蚀刻掉所述介质层（7）来定义岛屿多个（9）; 蚀刻掉所述叠层结构（4,5,6）以及使用所述基质细胞的薄的栅极氧化物层（3），以限定栅极区（10）氧化物冰岛（9）。

公开(公告)号：EP1017087A1

公开(公告)日：2000-07-05

申请号：EP98830794.8

申请日：1998-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cereda, Sergio Manlio ,  Caprara, Paolo

IPC: H01L21/265 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  Y10S438/976

Abstract: A process for manufacturing a MOS transistor (1) integrated in a semiconductor substrate (2) having a first type of conductivity, which process comprises the steps of:

forming a layer (3) of gate oxide over the semiconductor substrate (2);
forming a gate electrode (4) over this oxide layer;
forming a layer (5) of covering oxide over the gate oxide layer (3), the gate electrode (4), and around the gate electrode (4);
implanting a dopant of a second type of conductivity to provide implanted regions (6,6a,6b) adjacent to the gate electrode;
subjecting the semiconductor to thermal treatments to allow the implanted regions (6,6a,6b) to diffuse into the semiconductor substrate (2) under the gate electrode (4) and form gradual junction drain and source regions of said transistor.

Abstract translation: 一种集成在具有第一类导电性的半导体衬底（2）中的MOS晶体管（1）的制造方法，该工艺包括以下步骤：在半导体衬底（2）上形成栅极氧化物层（3）; 在该氧化物层上形成栅电极（4）; 在所述栅极氧化物层（3），所述栅电极（4）和所述栅电极（4）周围形成覆盖氧化物的层（5）。 注入第二类导电性的掺杂剂以提供与栅电极相邻的注入区域（6,6a，6b）; 对半导体进行热处理以允许注入区域（6,6a，6b）扩散到栅极（4）下方的半导体衬底（2）中，并形成所述晶体管的逐渐结的漏极和源极区域。

公开(公告)号：EP0902465A1

公开(公告)日：1999-03-17

申请号：EP97830427.7

申请日：1997-08-27

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cassio, Valerio ,  Caprara, Paolo ,  Cereda, Manlio Sergio

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: The invention relates to a process for manufacturing electronic virtual ground memory devices integrated on a semiconductor and including a matrix (3) of floating gate memory cells, the matrix being formed on a semiconductor substrate (10) with a plurality of continuous bit lines (7) extending across the substrate (10) as discrete parallel stripes. The matrix includes a circuit portion (C') for selection transistors (20), and the memory devices incorporating decode and address circuit portions (A,B) having P-channel and N-channel MOS transistors.
The inventive process comprises at least the following steps: forming N-wells (11) in at least one (A) of said substrate portions to accommodate said P-channel transistors, defining the active areas of all the transistors by means of a screening mask (33), and then growing an isolation layer (13) through the apertures of said mask (33). The active area definition mask (33) is not open over the matrix region (C'') of the memory cells.

Abstract translation: 本发明涉及一种用于制造集成在半导体上并包括浮动栅极存储单元的矩阵（3）的电子虚拟接地存储器件的方法，该矩阵形成在具有多个连续位线（7）的半导体衬底上 ）作为离散的平行条纹延伸穿过基底（10）。 该矩阵包括用于选择晶体管（20）的电路部分（C'），以及包括具有P沟道和N沟道MOS晶体管的解码和寻址电路部分（A，B）的存储器件。 本发明的方法至少包括以下步骤：在至少一个（A）所述衬底部分中形成N阱（11）以容纳所述P沟道晶体管，借助于屏蔽掩模限定所有晶体管的有效面积 （33），然后通过所述掩模（33）的孔生长隔离层（13）。 有源区域定义掩模（33）在存储器单元的矩阵区域（C“）上不开放。

公开(公告)号：EP0851493B1

公开(公告)日：2006-11-29

申请号：EP96830655.5

申请日：1996-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Camerlenghi, Emilio ,  Caprara, Paolo ,  Fontana, Gabriella, c/o SGS-Thomson

IPC: H01L27/00 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76838 ,  H01L2924/3011

公开(公告)号：EP0902466B1

公开(公告)日：2005-01-19

申请号：EP97830428.5

申请日：1997-08-27

Applicant: STMicroelectronics S.r.l.

Inventor： Cassio, Valerio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11541 ,  H01L27/11543

公开(公告)号：EP1032035B1

公开(公告)日：2004-10-13

申请号：EP99830100.6

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l. ,  Wafer Scale Integration, Inc.

Inventor： Pozzoni, Pierantonio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Irani, Ruston

IPC: H01L21/8247

CPC classification number: H01L27/11521

公开(公告)号：EP1220321A1

公开(公告)日：2002-07-03

申请号：EP00830851.2

申请日：2000-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： Vendrame, Loris ,  Caprara, Paolo ,  Oddone, Giorgio ,  Barcella, Antonio

IPC: H01L29/732 ,  H01L29/08

CPC classification number: H01L29/7322 ,  H01L29/0813

Abstract: The present invention relates a transistor comprising a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of said first type (P+) of conductivity inside said substrate region (14) and adjacent to a first terminal (C) of said transistor, a well (11) of second type (N) of conductivity placed inside said substrate region (14), characterized in that said well (11) of second type (N) of conductivity comprises at least a second contact region (12) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of said transistor, and a plurality of third contact regions (10) of said first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E1, ..., E3) of said transistor interposed each one (10) other (12) by proper insulating shapes (20).

Abstract translation: 本发明涉及一种晶体管，其包括在具有相同类型（P）导电性的半导体材料层中的第一类型（P）的基底区域（14），至少第一类型的第一接触区域（13） （14）内并与所述晶体管的第一端（C）相邻的电导率（P +），放置在所述衬底区域（14）内的第二类型（N）导电性阱（11），其特征在于： 所述第二类型（N）的导体的阱（11）包括与所述晶体管的第二端子（B）的区域相邻的至少第二接触区域（N）的第二接触区域（12），并且多个 与所述晶体管的第三端子（E1，...，E3）的多个区域相邻的所述第一类型导电性（P +）的第三接触区域（10）通过适当地插入每个（10）另一个（12） 绝缘形状（20）。

公开(公告)号：EP0902463A1

公开(公告)日：1999-03-17

申请号：EP97830433.5

申请日：1997-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Cassio, Valerio ,  Wurthwein, Arturo

IPC: H01L21/321 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/32139

Abstract: A method of manufacturing a plurality of floating gate regions lying parallel on a semiconductor substrate (10), and of inhibiting the formation of residue materiallaterally contiguous to each floating gate region, comprises the following steps: growing a thin oxide layer (13) over the semiconductor substrate (10); depositing a first layer (14) of polysilicon to fully cover the first thin oxide layer; growing and/or depositing an intermediate dielectric layer (15) over the first layer (14) of polysilicon; depositing a second layer (16) of polysilicon to fully cover the intermediate dielectric layer (15). This method further comprises the steps of depositing a final dielectric layer (17) to cover the previously deposited and/or grown layers (13,14,15,16); depositing a layer of resist onto the final dielectric layer, followed by a photolithographing step to define a planar geometry bounding the floating gate regions; and carrying out a first etching to only transfer this planar geometry onto the final dielectric layer (17), thereby producing a mask for a late second etching of the self-aligned type; thoroughly removing the layer of resist; carrying out a second self-aligned etching to spatially define the floating gate regions with a vertical profile.

Abstract translation: 制造浮在一个半导体衬底（10）位于平行的栅极区域中的多个方法，和残余材料尾盘反弹邻接的各浮栅区的形成，抑制的方法包括以下步骤：生长在一薄的氧化物层（13） 半导体衬底（10）; 沉积多晶硅完全覆盖第一薄氧化物层的第一层（14）; 生长和/或在多晶硅的第一层（14）中间介电层（15）上沉积; 沉积多晶硅的第二层（16）完全覆盖中间介电层（15）。 该方法还包括沉积最终介电层（17），以覆盖先前沉积和/或生长的层（13,14,15,16）的步骤; 沉积抗蚀剂层到最终的介电层，接着是步骤photolithographing以限定平面的几何形状界定浮栅区; 并进行第一蚀刻，以仅传输该平面的几何形状到最终的介电层（17），由此产生的自对准型的后期第二蚀刻的掩模; 彻底除去抗蚀剂的层; 进行第二自对准蚀刻到空间上与垂直轮廓限定在浮置栅极区域。