公开(公告)号：EP0915509B1

公开(公告)日：2005-12-28

申请号：EP97830543.1

申请日：1997-10-24

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Bolognesi, Davide ,  Magri', Angelo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238

Abstract: Process for integrating in a same MOS technology devices with different threshold voltages, characterized by comprising the steps of: simultaneously forming on a semiconductor material layer (2,2') of at least two gate electrodes (5,5';10,10') for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density for unit area; selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions (7;7') for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions, and said two MOS devices consequently have respective threshold voltages that depend on the corner density for unit area and on the aperture angles of the corner of the respective gate electrodes.

公开(公告)号：EP1335507B1

公开(公告)日：2005-09-14

申请号：EP02425043.3

申请日：2002-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Coffa, Salvatore ,  Frisina, Ferruccio

IPC: H04B10/00

CPC classification number: H04B10/801

公开(公告)号：EP1420457A1

公开(公告)日：2004-05-19

申请号：EP02425695.0

申请日：2002-11-14

Applicant: STMicroelectronics S.r.l.

Inventor： Magri, Angelo ,  Frisina, Ferruccio

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66719 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/872

Abstract: A process for integrating a Schottky contact to the drain inside the apertures of the elementary cells that constitute the integrated structure of an insulated gate power device in a totally self-alignment manner comprises the formation of a trench in said apertures by anisotropic etching using dielectric spacers. Therefore this process does not require a dedicated masking step. This overcomes the limits to the possibility of increasing the packing density of the cellular structure of the integrated power device, while permitting improved performances of the co-integrated Schottky diode under inverse polarization of the device and producing other advantages.
A planar integrated insulated gate power device with high packing density of the elementary cells that compose it, having a Schottky diode electrically in parallel to the device, is also disclosed.
In all devices the drain region under the Schottky contact is bounded by oppositely doped diffusion regions to shield electrical fields.
A specific device includes an implanted buried region having a high resistivity located in the drain under the Schottky contact and at a greater depth than the trench.

Abstract translation: 将肖特基接触集成到构成绝缘栅功率器件的全部自对准方式的集成结构的元件单元的孔内的漏极的工艺包括通过各向异性蚀刻在所述孔中形成沟槽，使用介质间隔物 。 因此，该过程不需要专门的掩蔽步骤。 这克服了增加集成功率器件的蜂窝结构的封装密度的可能性的限制，同时可以在器件的反极化下提高共同整合的肖特基二极管的性能并产生其它优点。 还公开了一种具有构成其的单元电池的高封装密度的平面集成绝缘栅功率器件，其具有与器件并联的肖特基二极管。 在所有器件中，肖特基接触下的漏极区域被相反掺杂的扩散区域限制，以屏蔽电场。 具体的器件包括位于肖特基接触之下的漏极中并具有比沟槽更深的深度的具有高电阻率的注入掩埋区。

公开(公告)号：EP0817274B1

公开(公告)日：2004-02-11

申请号：EP96830384.2

申请日：1996-07-05

Applicant: STMicroelectronics S.r.l.

Inventor： Magri', Angelo ,  Zambrano, Raffaele ,  Frisina, Ferruccio

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66712

Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

公开(公告)号：EP1335507A1

公开(公告)日：2003-08-13

申请号：EP02425043.3

申请日：2002-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario ,  Coffa, Salvatore ,  Frisina, Ferruccio

IPC: H04B10/00

CPC classification number: H04B10/801

Abstract: The invention relates to a method and an isolation device for providing optimum galvanic isolation between two low-voltage electronic devices (A,B), with the devices (A,B) being optically coupled together. The isolation device is essentially an opto-electronic integrated structure comprising a waveguide (17) that is formed between two separate circuit portions integrated in respective regions (13,13') of the same semiconductor substrate.
Thus, the circuit portions (A,B) are fully galvanically isolated from each other, while the optical signal is transmitted therebetween through an integrated waveguide that is photolithographically patterned in the semiconductor.

Abstract translation: 本发明涉及一种方法和设备，用于提供最佳的电流隔离两个低电压电子设备（A，B）之间，与所述设备（A，B）光学耦合在一起的隔离。 隔离装置是本质上对光电集成结构，其包括波导（17）那样被集成在同一半导体衬底的respectivement区域（13,13“）两个独立的电路部分之间形成。 因此，电路部（A，B）是完全流电隔离海誓山盟，而光信号是通过对集成波导之间的反式mitted有眼在半导体光刻图案化。

公开(公告)号：EP0961325A1

公开(公告)日：1999-12-01

申请号：EP98830321.0

申请日：1998-05-26

Applicant: STMicroelectronics S.r.l.

Inventor： Magri' Angelo ,  Frisina, Ferruccio

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7802

Abstract: High density MOS technology power device structure, comprising body regions (31A-31D) of a first conductivity type formed in a semiconductor layer (1) of a second conductivity type, characterized in that said body regions comprise at least one plurality of substantially rectilinear and substantially parallel body stripes (32) each joined at its ends to adjacent body stripes (32) by means of junction regions (33), so that said at least one plurality of body stripes (32) and said junction regions (33) form a continuous, serpentine-shaped body region (31A-31D).

Abstract translation: 高密度MOS技术功率器件结构，包括形成在第二导电类型的半导体层（1）中的第一导电类型的主体区域（31A-31D），其特征在于，所述主体区域包括至少多个基本上直线和 大体上平行的主体条（32）各自通过结区（33）在其端部连接到相邻的主体条（32），使得所述至少一个多个体条（32）和所述连接区（33）形成 连续的蛇形体区域（31A-31D）。

公开(公告)号：EP1873837A1

公开(公告)日：2008-01-02

申请号：EP06425448.5

申请日：2006-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Murabito, Domenico ,  Frisina, Ferruccio

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L21/329 ,  H01L21/336 ,  H01L29/417 ,  H01L29/08 ,  H01L21/20 ,  H01L21/324 ,  H01L29/739 ,  H01L29/872 ,  H01L29/732

CPC classification number: H01L29/7811 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A process for manufacturing a semiconductor power device envisages the steps of: providing a body (3) made of semiconductor material having a first top surface (3a); forming an active region (4a; 29, 30) with a first type of conductivity in the proximity of the first top surface (3a) and inside an active portion (1a) of the body (3); and forming an edge-termination structure (4b, 5). The edge-termination structure is formed by: a ring region (5) having the first type of conductivity and a first doping level, set within a peripheral edge portion (1b) of the body (3) and electrically connected to the active region; and a guard region (4b), having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface (3a) and connecting the active region (4a; 29, 30) to the ring region (5). The process further envisages the steps of: forming a surface layer (9) having the first type of conductivity on the first top surface (3a), also at the peripheral edge portion (1b), in contact with the guard region; and etching the surface layer (9) in order to remove it above the edge portion (1b) in such a manner that the etch terminates inside the guard region (4b).

Abstract translation: 一种用于制造半导体功率器件的工艺设想的以下步骤：提供由半导体材料制成的本体（3），其具有第一顶表面（3a）的; 形成于有源区（4a中; 29，30）与所述第一顶表面（3a）的附近的第一导电类型和内部向身体的活性部分（1a）中（3）; 和边缘终端结构的形成（图4b，5）。 边缘终端结构通过以下步骤形成：（5）具有第一导电类型和第一掺杂水平，外围边缘部分内设置一个环区（1b）的所述主体（3）和电连接到所述有源区; 和一个保护区（4b）的具有第一类型导电性的和第二掺杂水平，比所述第一掺杂水平较高，在所述第一顶表面（3a）的附近设置和连接所述有源区（4a中; 29，30 ）到环形区域（5）。 该方法进一步设想如下步骤：形成具有第一顶表面（3a）的所述第一导电类型的表面层（9），所以在周缘部分（1b）中，在与所述保护区接触; 并且为了蚀刻所述表面层（9），以寻求的方式没有蚀刻除去其边缘部分（1b）中上方的防护区域内终止（4b）中。

公开(公告)号：EP1742250A1

公开(公告)日：2007-01-10

申请号：EP05425496.6

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate (10,11) comprising a wide band gap superficial semiconductor layer (11), the method comprising the steps of:
- forming a screening structure (12) on the superficial semiconductor layer (11) comprising at least one dielectric layer (12) which leaves a plurality of areas of the superficial semiconductor layer (11) exposed,
- carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer (11) for forming at least one deep implanted region (14a),
- carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer (11) for forming at least one implanted body region (16) of the MOS transistor aligned with the deep implanted region (14a),
- carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer (11) for forming at least an implanted source region (18) of the MOS transistor inside the at least one implanted body region (16), the method comprising an activation thermal process of the first type and second type of low thermal budget dopant suitable to complete said formation of the body region (16), of the source region (18) and of the deep implanted region (14a).

Abstract translation: 一种用于在包括宽带隙表面半导体层（11）的宽带隙半导体衬底（10,11）上制造垂直功率MOS晶体管的方法，所述方法包括以下步骤： - 在表面上形成屏蔽结构（12） 包括至少一个电介质层（12）的半导体层（11），所述至少一个电介质层（12）使所述表面半导体层（11）的多个区域暴露， - 在所述表面半导体层中执行至少第一类型掺杂剂的第一离子注入 （11），用于形成至少一个深注入区域（14a）， - 在所述表面半导体层（11）中执行所述第一类型掺杂物的至少第二离子注入，以形成至少一个注入体区域（16）， 所述MOS晶体管与所述深注入区域（14a）对准， - 在所述表面半导体层（11）中执行至少一次第二类型掺杂物的离子注入，以形成至少一个注入源区域 所述方法包括适于完成所述体区（16）的所述形成的所述第一类型和第二类型低热预算掺杂物的激活热过程， ），源极区域（18）和深注入区域（14a）。

公开(公告)号：EP1696490A1

公开(公告)日：2006-08-30

申请号：EP05425102.0

申请日：2005-02-25

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio

IPC: H01L29/78

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095

Abstract: Compensation power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising:

a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100),
a column region (50) of the second type of conductivity realised in said semiconductor layer (20) below the body region (40),

wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21,22,23,24), overlapped on each other, wherein the resistivity of each layer is different from that of the other layers and in that said column region (50) comprises a plurality of doped sub-regions (51,52,53,54), each realised in one of said semiconductor layers (21,22,23,24), wherein the dopant concentration of each doped sub-region (51,52,53,54) is such as to realise a balance between the total amount of charge of a first conductivity type and of a second conductivity type in each couple of layers and subregions.

Abstract translation: 集成在包括多个元件单元的第一导电类型的半导体衬底（100）上的补偿电力电子器件（30），每个元件单元包括：在半导体层上实现的第二导电类型的体区（40） 在所述半导体衬底（100）上形成的所述第一类型导电体的导体（20），在所述半导体层（20）中实现的所述第二导电类型的列区域（50），其中所述半导体层 （20）包括彼此重叠的多个半导体层（21,22,23,24），其中每个层的电阻率不同于其它层的电阻率，并且所述列区域（50）包括多个 的掺杂子区域（51,52,53,54），其分别在所述半导体层（21,22,23,24）中的一个中实现，其中每个掺杂子区域（51,52,53， 54）实现了af的总费用之间的平衡 第一导电类型和第二导电类型在每对层和子区域。

公开(公告)号：EP1058303A1

公开(公告)日：2000-12-06

申请号：EP99830334.1

申请日：1999-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/266

CPC classification number: H01L29/7802 ,  H01L21/266 ,  H01L29/1095 ,  H01L29/66712

Abstract: A process for fabricating a VDMOS structure comprising the steps of forming a body region of a first conductivity type (p-) by implanting and diffusing a dopant (B) through a first aperture defined by the edges of a patterned gate conductor layer (4) on a dielectric gate layer (3) formed on the surface of an epitaxial layer (n). forming region (p+) with a higher dopant concentration within said body region (p-) by implanting dopant at a high kinetic energy down to a certain depth from the surface of the epitaxial layer, implanting and diffusing source regions of a second conductivity type (n+) in said body region (p-) projectively above said region of higher doping level (p+), comprises the following steps:

forming a resist mask (Ms) defining apertures for implanting said source regions prior to the formation of said region (p+) of higher doping level:
implanting through said resist mask (Ms), said dopant of a second conductivity type (n+) in a superficial zone of said body region (p-). and a dopant of said first conductivity type at a kinetic energy sufficient to implant the dopant (p+) at a depth below said superficial zone implanted with a dopant (n-) of the second conductivity type;
annealing at a temperature and for a time sufficient to form (n+) source/ (p-) body junctions above body regions (p+) of a relatively high dopant concentration (p+).

An effective reduction of the gain of the parasite transistor is achieved without the need of a dedicated masking step.

Abstract translation: 一种用于制造VDMOS结构的方法，包括以下步骤：通过将掺杂剂（B）通过由图案化的栅极导体层（4）的边缘限定的第一孔注入和扩散而形成第一导电类型（p-）的体区， 在形成在外延层（n）的表面上的电介质栅极层（3）上。 通过以高动能将掺杂剂注入到距离外延层的表面一定深度的方式，在所述体区（p-）中具有较高掺杂剂浓度的形成区（p +），注入和扩散第二导电类型的源区（ n +）在所述体积区域（p-）中高于所述掺杂浓度较高的区域（p +），包括以下步骤：形成在形成所述区域（p +）之前形成用于注入所述源极区域的孔的抗蚀剂掩模（Ms） ）：通过所述抗蚀剂掩模（Ms），在所述体区（p-）的表面区域中注入第二导电类型（n +）的所述掺杂剂。 和所述第一导电类型的掺杂剂，其动能足以在注入第二导电类型的掺杂剂（n-）的所述浅表区下方的深度处注入掺杂剂（p +）; 在足以在较高掺杂剂浓度（p +）的体区（p +）之上形成（n +）源/（p-）体结的温度和时间退火。 实现了寄生晶体管的增益的有效减少，而不需要专门的掩蔽步骤。