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    Nonvolatile memory device
    12.
    发明公开
    Nonvolatile memory device 审中-公开
    非易失性存储设备

    公开(公告)号：EP1865513A1

    公开(公告)日：2007-12-12

    申请号：EP06115912.5

    申请日：2006-06-22

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Asia Pacific Pte Ltd. ,  Hynix Semiconductor Inc.

    Inventor： Song, Dae Sik ,  Park, Jaeseok ,  Mulatti, Jacopo

    IPC: G11C16/10

    CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

    Abstract: With the proposed page buffer, noise or eventual voltage surges on the source line do not cause fails of program operations and it is finally made possible to store a bit to be written in a cell of a page of the memory device while a program operation is in progress on a different page with the fullest reliability.
    The cache latch is isolated from the source line during program operations and during program-verify operations. Moreover, the main latch and the cache latch are not directly connected, but are coupled through a temporary latch that is used for transferring data from the cache latch to the main latch. Eventual noise or voltage surges present on the source line of a selected bitline cannot flip the bit stored in the cache latch because the cache latch is not connected to the source line during a program or program-verify operations, but the bit stored therein is transferred to the source line through a temporary latch.

    Abstract translation: 利用所提出的页面缓冲器，源线上的噪声或可能的电压浪涌不会导致程序操作失败，并且最终有可能在编程操作是存储一位以写入存储器设备的页面的单元中 以最充分的可靠性在不同的页面上进行。 在编程操作期间和编程验证操作期间，高速缓存锁存器与源极线隔离。 而且，主锁存器和高速缓存锁存器不是直接连接的，而是通过临时锁存器耦合的，该临时锁存器用于将数据从高速缓存锁存器传输到主锁存器。 在选定位线的源极线上出现的最终噪声或电压浪涌不能翻转存储在高速缓存锁存器中的位，因为在程序或编程验证操作期间高速缓存锁存器未连接到源线，但存储在其中的位被传送 通过临时锁存器连接到源代码行。

    A method of programming and verifying cells of a nonvolatile memory and relative nand flash memory
    13.
    发明公开
    A method of programming and verifying cells of a nonvolatile memory and relative nand flash memory 有权
    一种用于编程和非易失性存储器的单元的验证方法和相应的NAND闪速存储器

    公开(公告)号：EP1772873A1

    公开(公告)日：2007-04-11

    申请号：EP05425712.6

    申请日：2005-10-10

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Asia Pacific Pte Ltd. ,  Hynix Semiconductor Inc.

    Inventor： Jeong, Kuhong ,  Lee, Hyungsang ,  Mulatti, Jacopo

    IPC: G11C16/34

    CPC classification number: G11C16/3459 ,  G11C16/3454 ,  G11C29/832 ,  G11C2216/14

    Abstract: A method of programming cells of a destination page of a nonvolatile memory and verifying whether logic values stored in programmed cells of a source page of the same memory have been correctly copied into corresponding cells of the destination page, exploits both the fast but inadequate-at-times Global Verify operation and, if the Global Verify operation fails for a certain number of attempts, the Byte-by-byte Verify operation, which is slower but accurate.

    Abstract translation: 编程非易失性存储器的一个目的地页的单元，并验证是否存储在同一存储器的源页面的编程单元的逻辑值havebeen正确复制到目标页面的相应小区，攻击两者的方法几乎但不足-在 -times全球验证操作，并且如果全球验证尝试的一定数目的手术失败，则逐字节验证手术，所有这一切是速度较慢，但​​准确的。

    Basic stage for a charge pump circuit
    15.
    发明公开
    Basic stage for a charge pump circuit 有权
    BasisstufefürLadungspumpeschaltung

    公开(公告)号：EP1349264A1

    公开(公告)日：2003-10-01

    申请号：EP02425199.3

    申请日：2002-03-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Nuzzarello, Giovanni ,  Mulatti, Jacopo

    IPC: H02M3/07 ,  G11C5/14 ,  G05F3/20

    CPC classification number: H02M3/073 ,  G11C5/145 ,  H02M2003/071

    Abstract: It is describes a basic stage for a charge pump circuit having at least an input terminal (UP) and an output terminal (DOWN) and comprising:

    at least a first inverter inserted between said input and output terminals (UP, DOWN) and comprising a first complementary pair of transistors (MP1, MN1), defining a first internal node (XL),
    at least a second inverter inserted between said input and output terminals (UP, DOWN) and comprising a second complementary pair of transistors (MP2, MN2), defining a second internal node (XR),
    respective first and second capacitors (CL, CR) connected to said first and second internal nodes (XL, XR) and receiving a first and second driving signals (CK, CK_N);
    the first (MP1, MN1) and second (MP2, MN2) pairs of transistors having the control terminals cross-connected to the second (XR) and first (XL) internal node.
    Advantageously according to the invention, the basic stage comprises at least a first biasing structure (12) connected to the first and second internal nodes (XL, XR) and comprising a first (MN3) and second (MN4) biasing transistors, which are respectively coupled to said first and second inverters.

    Abstract translation: 描述了具有至少输入端（UP）和输出端（DOWN）的电荷泵电路的基本阶段，并且包括：至少插入在所述输入和输出端子（UP，DOWN）之间的第一逆变器，并且包括： 限定第一内部节点（XL）的第一互补对晶体管（MP1，MN1），至少插入在所述输入和输出端子（UP，DOWN）之间并包括第二互补晶体管对（MP2，MN2） ，限定第二内部节点（XR），连接到所述第一和第二内部节点（XL，XR）的相应的第一和第二电容器（CL，CR）并接收第一和第二驱动信号（CK，CK_N）; 具有与第二（XR）和第一（XL）内部节点交叉连接的控制端的第一（MP1，MN1）和第二（MP2，MN2）晶体管对。 有利地，根据本发明，基本级包括至少连接到第一和第二内部节点（XL，XR）的第一偏置结构（12），并且包括第一（MN3）和第二（MN4）偏置晶体管 ，其分别耦合到所述第一和第二逆变器。

    Fast programming method for nonvolatile memories, in particular flash memories, and related memory architecture
    16.
    发明公开
    Fast programming method for nonvolatile memories, in particular flash memories, and related memory architecture 有权
    为非易失性存储器，尤其是闪速存储器，以及类似的存储器架构快速编程方法

    公开(公告)号：EP1308964A1

    公开(公告)日：2003-05-07

    申请号：EP01830671.2

    申请日：2001-10-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Lomazzi, Guido ,  Mulatti, Jacopo ,  Surico, Stefano

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C2216/14 ,  G11C2216/16

    Abstract: The programming method includes the following steps: sequentially receiving (23, 27) a plurality of data words; temporarily storing (24, 29) each data word after its reception; and simultaneously writing (31, 35) in parallel the plurality of stored data words in a memory array. After reception and temporary storage of each data word, the memory increments (25) an address counter and sends a "ready" signal (26). Upon reception of each new data word (27), the memory verifies whether the address associated thereto is in the same sector as the initial data word (28) and whether n data words have already been stored (30). If the sector is different, blind-programming step is terminated (35, 36) and the verifying is carried out (37); if the sector is the same but n data words have already been stored temporarily, the memory writes the temporarily stored words in the memory array (31), updates the address counter (25), and then sends the "ready" signal (26).

    Abstract translation: 该编程方法包括以下步骤：顺序地接收（23，27）的数据字的多个; 暂时存储（24，29）其接收之后每个数据字; 同时，并与存储数据字的在存储器阵列中的多个书写（31，35）并联连接。 接收和每个数据字的临时存储之后，存储器增量（25），以解决计数器并发送一个“就绪”信号（26）。 在每个新的数据字（27）的接收，所述存储器确认是否在其上的地址相关联是在相同的扇区，不论数据字已经被存储的所述初始数据字（28）和n（30）。 如果该扇区是不同的，盲的编程步骤被终止（35，36）和所述验证被执行（37）; 如果该扇区是相同的，但n个数据字已经被暂时存储，存储器写入所述存储器阵列中的暂时存储字（31）更新地址计数器（25），然后发送“准备”信号（26） ，

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