Abstract:
A memory device includes a plurality of memory cells (3), arranged in row and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V A ); a column addressing circuit (4) for addressing a bit line (12) corresponding to a memory cell (3) to be read; and a row addressing circuit (5) for addressing a word line (13) corresponding to the memory cell (3) to be read. Moreover, the column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the memory cell (3) to be read substantially at the supply voltage (V A ).
Abstract:
A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor (20) of chalcogenic material furnishing an electrical quantity (V(T), I(T)) that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed (21) so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor (20) has the same structure as a memory cell and is programmed with precision, preferably in the reset state.