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    Method for reading a multiple-level memory cell
    13.
    发明公开
    Method for reading a multiple-level memory cell 失效
    Verfahren zum Lesen einer Mehrbitspeicherzelle

    公开(公告)号：EP0945869A1

    公开(公告)日：1999-09-29

    申请号：EP98830188.3

    申请日：1998-03-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Maloberti, Franco ,  Oneto, Andrea ,  Torelli, Guido

    IPC: G11C11/00 ,  G11C11/56

    CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C11/5642

    Abstract: Method (200) for reading a multiple-level memory cell (C 12 ) capable of taking on three or more states which are represented by different values of a physical quantity (Icell) and each of which is associated with a corresponding logical value (LVcell), comprising the steps of setting (210) an actual physical quantity (Is 1 ) to a value correlated with the value of the physical quantity (Icell) corresponding to the state of the memory cell (C 12 ), and repeating (235), up to the complete determination of the logical value (LVcell) corresponding to the state of the memory cell (C 12 ), a cycle (215-235) comprising the steps of setting (227, 232) a component of the logical value (D i ) to a value which is a function of a range in which the actual physical quantity (Is i ) lies, determined by comparing (215, 220) the actual physical quantity (Is i ) with at least one reference physical quantity (Ir i ) having a predetermined value lying between a minimum value and a maximum value for the actual physical quantity (Is i ), and setting (237) the actual physical quantity for a possible next cycle (Is (i+1) ) to a relative value of the actual physical quantity (Is i ) with respect to the range in which it lies.

    Abstract translation: 用于读取能够承受三个或更多个状态的多级存储单元（C12）的方法（200），其由物理量（Icell）的不同值表示，并且每个与相应的逻辑值（LVcell）相关联， 包括以下步骤：将实际物理量（Is1）设置为与存储单元（C12）的状态对应的物理量（Icell）的值相关的值，并重复（235），直到 对与存储单元（C12）的状态相对应的逻辑值（LVcell）的完全确定，包括将逻辑值（Di）的分量设置为（227,232）的步骤的周期（215-235） 通过将实际物理量（Isi）与具有预定值之间的至少一个参考物理量（Iri）进行比较（215,220）来确定实际物理量（Isi）所在的范围的函数的值， 实际物理的最小值和最大值 数量（Isi）和将可能的下一个周期的实际物理量（Is（i + 1））设置为实际物理量（Isi）相对于其所在的范围的相对值。

    Fast reading, low power consumption memory device and reading method thereof
    16.
    发明公开
    Fast reading, low power consumption memory device and reading method thereof 有权
    存储器阵列具有快速读出操作和更低的功耗和相应的读出方法

    公开(公告)号：EP1548745A1

    公开(公告)日：2005-06-29

    申请号：EP04106858.6

    申请日：2004-12-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Torelli, Guido

    IPC: G11C11/34 ,  G11C8/10 ,  G11C7/12

    CPC classification number: G11C7/12 ,  G11C8/08

    Abstract: A memory device having a reading configuration and including a plurality of memory cells (3), arranged in rows and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V DD ); a column addressing circuit (4) and a row addressing circuit (5) for respectively addressing a bit line (12) and a word line (13) corresponding to a memory cell (3) selected for reading in the reading configuration. The column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the selected memory cell (3) substantially at the supply voltage (V DD ) in the reading configuration. A row driving circuit (6) biases the addressed word line (13) corresponding to the selected memory cell (3) at a non-zero word line read voltage (V WL ), so that a predetermined cell voltage (V CELL ), lower than a phase change voltage (V PHC ), is applied between the first terminal (3a) and the second terminal (3b) of the selected memory cell (3) in the reading configuration.

    Abstract translation: 具有读取配置和包含存储单元的多个（3），以行和列排列的存储器单元的存储器装置（3）布置在具有连接到相同的位线respectivement第一端子（3a）中同一列（12）中 和存储单元（3），布置在同一行上具有respectivement第二端子（3b）中选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VDD）; 一列寻址电路（4）和用于分别寻址的位线（12）和字线（13）的行寻址电路（5）对应于一个存储单元（3）选择用于在读取配置读取。 列寻址电路（4）被配置为偏置对应于所选择的存储单元的寻址位线（12）（3）在基本上在读取配置中的电源电压（VDD）。 行驱动电路（6）偏压对应于所述选定存储器单元被寻址的字线（13）（3）在非零字线读取电压（VWL），所以没有在预定的电池电压（V电池），比下 相变电压（VPHC）在第一端（3a）和在读取配置所述选定存储器单元（3）的第二端（3b）的之间。

    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device
    19.
    发明公开
    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device 有权
    在非易失性更通常高密度存储器和相关联的换能器为模拟/数字转换的方法

    公开(公告)号：EP1211812A3

    公开(公告)日：2003-02-12

    申请号：EP00127649.2

    申请日：2000-11-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

    IPC: H03M1/14 ,  G11C11/56

    CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

    Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg). The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB). The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.

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