公开(公告)号：EP0696839B1

公开(公告)日：1998-02-25

申请号：EP94830402.7

申请日：1994-08-12

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pulvirenti, Francesco ,  Gariboldi, Roberto

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M3/07

公开(公告)号：EP0743529A1

公开(公告)日：1996-11-20

申请号：EP95830204.4

申请日：1995-05-16

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME.

Inventor： Pulvirenti, Francesco ,  Gariboldi, Roberto

IPC: G01R31/02 ,  G05B19/042

CPC classification number: G01R31/026 ,  G05B19/0423

Abstract: The invention relates to a method for detecting an open load by means of a driver having at least one main power transistor (M10) connected to the load (L) and one auxiliary transistor (M11) connected in parallel with the main transistor (M10) between a first power supply voltage reference (Vs) and a second voltage reference (GND), the method providing a comparison between a first voltage (V IN1 ) present on a terminal (S10) connected to the load of the main transistor (M10) and a second voltage (V IN2 ) present on a terminal (S11) of the auxiliary transistor (M11).
The invention also relates to a circuit for detecting an open load (L), in which the said method is implemented.

Abstract translation: 本发明涉及一种通过驱动器检测开路负载的方法，所述驱动器具有连接到负载（L）的至少一个主功率晶体管（M10）和与主晶体管（M10）并联连接的一个辅助晶体管（M11） 在第一电源电压基准（Vs）和第二电压基准（GND）之间，提供与存在于连接到主晶体管（M10）的负载的端子（S10）上的第一电压（VIN1）和 存在于辅助晶体管（M11）的端子（S11）上的第二电压（VIN2）。 本发明还涉及一种用于检测开启负载（L）的电路，其中实现了所述方法。

公开(公告)号：EP0696839A1

公开(公告)日：1996-02-14

申请号：EP94830402.7

申请日：1994-08-12

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pulvirenti, Francesco ,  Gariboldi, Roberto

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M3/07

Abstract: The present invention relates to a charge pump MOS voltage booster and to two applications where said type of booster can find advantageous use.
The voltage booster comprises instead of the classical diodes, which exhibit undesired voltage drop, four MOS transistors and, instead of the classical single-output oscillator with associated charge transfer condenser, an oscillator with two outputs and two corresponding charge transfer condensers.
In this manner there are practically no undesired voltage drops and the ripple is reduced without complicating the circuitry structure.

Abstract translation: 本发明涉及一种电荷泵MOS电压升压器和两种应用，其中所述类型的升压器可以发现有利的用途。 升压器包括代替典型的二极管，其表现出不希望的电压降，四个MOS晶体管，而不是经典的具有相关电荷转移电容器的单输出振荡器，具有两个输出的振荡器和两个相应的电荷转移电容器。 以这种方式，实际上没有不期望的电压降并且纹波减小而不使电路结构复杂化。 $$

公开(公告)号：EP1414011A1

公开(公告)日：2004-04-28

申请号：EP02425638.0

申请日：2002-10-22

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Sala, Leonardo ,  Domanin, Daniele ,  Gariboldi, Roberto ,  Ilardo, Santo

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3622 ,  G09G2310/0213 ,  G09G2330/021

Abstract: The present invention refers to a method for scanning sequence selection for displays.
In one embodiment of the method for scanning sequence selection for displays having a plurality of rows and columns, said plurality of rows and columns cross each other defining a plurality of optical elements having a first optical state and a second optical state in response to a first electric state and to a second electric state. The method comprises the phases of driving said plurality of row of said display according to a prefixed scanning ordering. The method is characterized in that said prefixed scanning ordering is predisposed by ordering every column of said plurality of column so that the total switching number between said first electric state and said second electric state is minimized.

Abstract translation: 预定义扫描排序通过对显示器的每一列进行排序而使电气状态之间的总切换次数最小化。

公开(公告)号：EP0909030B1

公开(公告)日：2004-02-25

申请号：EP97830506.8

申请日：1997-10-10

Applicant: STMicroelectronics S.r.l.

Inventor： Genova, Angelo ,  Gariboldi, Roberto ,  Cantone, Giuseppe

IPC: H03K3/0232 ,  H03K3/355

CPC classification number: H03K3/011 ,  H03K3/0232 ,  H03K3/355

公开(公告)号：EP1341150A1

公开(公告)日：2003-09-03

申请号：EP02425109.2

申请日：2002-02-28

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Rodeschini, Luca ,  Sala, Leonardo ,  Gariboldi, Roberto

IPC: G09G3/36

CPC classification number: G09G3/3625 ,  G09G3/2014 ,  G09G3/3622 ,  G09G2330/021

Abstract: Herein described is a driving method for LCD modules having a multiplicity of display elements placed in the intersections of a matrix having a plurality of row electrodes and a plurality of column electrodes. The method comprises a first phase for scanning all the row electrodes of said matrix in an interval of scanning time (NT). The first phase comprises a second phase comprising the generation of a first signal suited to energizing at least one row electrode of the matrix for a first preset interval of time (T), the generation of second signals (C3(t), C5(t)) suited to energizing respectively each column electrode of said matrix simultaneously with the energizing of at least one row electrode. The second signals (C3(t), C5(t)) are suited to determining the grey level of each display element of at least one row electrode energized by means of an alternance of corresponding values distinct signal levels (Von, Voff, V1-V3) for intervals of time (T1on, T1off) comprised in the first preset interval of time (T) by means of a first PWM modulation. The first preset interval of time (T) is lower than the interval of scanning time (NT). The first phase comprises a third phase successive to the second phase and comprising the generation of another first signal suited to energizing at least another row electrode of said matrix for a second preset period of time (T) equal and successive to the first preset interval of time, the generation of third signals (C3(t), C5(t)) suited to energizing each column electrode of the matrix simultaneously to said at least another row electrode; the third signals are suited to determining the grey level of each display element of at least another row electrode energized by means of an altemance of values corresponding to said distinct signal levels (Von, Voff, V1-V3) for intervals of time (T2on, T2off) comprised in said second preset interval of time (T) by means of a second PWM modulation. The second PWM modulation is such to ensure the continuity of the signal level of said second signals (C3(t), C5(t)) and third signals (C3(t), C5(t)) in the passage from the first preset period of time (T) to the second preset period of time (T). (Figure 5).

Abstract translation: 快来描述的是一种用于驱动具有在具有电极行的多个部分并加以电极柱的多个A矩阵的交叉点放置显示元件的多个液晶显示模块的方法。 该方法包括在扫描时间（NT）间隔扫描电极与上述矩阵的所有行中的第一阶段。 所述第一相包含第二相，其包括适合于激励所述矩阵的至少一个行电极对的时间（T）的第一预设间隔的第一信号的产生，第二信号（C 3（t）的，C5（T的产生 ））适合于分别与至少一个行电极的通电同时激励所述矩阵的每一列电极。 第二信号（C 3（t）的，C5（t））的适合于所确定的采矿由对应值的alternance手段通电的至少一个行电极的每个显示元件的灰度级不同信号电平（从，V关闭，V1 V3）为在时间（T）由第一PWM调制手段的第一预设间隔由时间（T1ON，T1off）区间。 时间的第一预设时间间隔（T）比的扫描时间（NT）的时间间隔低。 所述第一相包含第三相连续的第二相和包含至少适合于激励所述矩阵的另一行电极的时间（T）相等，并且连续到的所述第一预定间隔的第二预设时间段的另一第一信号的生成 时间，（C 3（t）的，C5（t））的适合于同时激励所述矩阵的每一列电极到所述至少另一行电极产生第三信号的; 第三信号适合于所确定的采矿由对应于所述不同信号电平值的altemance手段（通电至少另一行电极的每个显示元件的灰度级（从，V关闭，V1-V3），用于时间T2ON的间隔， T2off）由第二PWM调制的机构，在上述由时间（T）的第二预设时间间隔。 第二PWM调制正在寻求确保的信号电平的连续性，所述第二信号（C3（t）的，C5（t））和第三信号（C3（t）的，C5（T））在从所述第一预设通道 的时间周期（T）时间的第二预设时间段（T）。 （图5）。

公开(公告)号：EP1324304A1

公开(公告)日：2003-07-02

申请号：EP01830810.6

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： Sala, Leonardo ,  Pulvirenti, Francesco ,  Gariboldi, Roberto

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G3/3622 ,  G09G2330/023

Abstract: The present invention refers to a supply system of the driving voltage generator of the rows and of the columns of a liquid crystal display. The supply system comprises first and second generator circuits (D3,D4) which output respective prefixed voltages (V3,V4). Each generator circuit receives two supply voltages. The first generator receives, via one voltage supply terminal, a first voltage (VLCD). The second generator receives, via one voltage supply terminal, a second voltage (GND). The other supply terminals of the generators are each connected to a charge storage device (CTNK), e.g. a capacitor, which acts as a charging tank. Charge stored in the capacitor is shared by both generators, and a control circuit (CONT) causes the voltage across the capacitor to lie within a predefined range.

Abstract translation: 本发明涉及到行的驱动电压产生器的供给系统和液晶显示器的列的。 所述供应系统包括第一和第二发生器电路（D3，D4）哪个输出respectivement前缀电压（V3，V4）。 每个发生器电路接收两个电源电压。 第一发生器接收，经由一个电压提供端，第一电压（VLCD）。 第二生成器接收，经由一个电压源端，第二电压（GND）。 发电机的另一电源端子分别连接到电荷存储装置（CTNK），例如 电容器，其用作一个充电罐。 存储在电容器的电荷被两个发生器共享;以及控制电路（CONT）使电容器两端的电压，使之处于预定范围内。

公开(公告)号：EP1182637A1

公开(公告)日：2002-02-27

申请号：EP00830587.2

申请日：2000-08-22

Applicant: STMicroelectronics S.r.l. ,  TECDIS S.p.A.

Inventor： Gariboldi, Roberto ,  Lavorerio, Riccardo ,  Sala, Leonardo ,  Nidasio, Giovanni

IPC: G09G3/36 ,  G09G5/36

CPC classification number: G09G5/395 ,  G09G3/3611 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/0278 ,  G09G2360/02 ,  G09G2360/12

Abstract: Presented is a new memory controller for use in a display, such as a liquid crystal display of the type comprising a set of first drivers (24), and a set of second drivers (26), a portion of which can be converted to said first drivers (26b). Also included is a RAM memory (62) structured to accept data at an input and output said data to the sets of first (24) and second (26) drivers when a master clock signal is received at said RAM memory (62). The memory controller includes a clock signal generator structured to generate said master clock signal; and a control signal generator circuit structured to generate control signals for said RAM memory (62) and said sets of first (24) and second (26) drivers. An important advantage to this memory controller is that it includes a set of auxiliary registers (52) structured to temporarily store a first portion of said data received from said RAM memory (62) after receiving a slave clock cycle, and said set of auxiliary registers (52) structured to output said first portion of data into said portion of said second drivers converted to said first drivers (26b) after receiving said master clock signal. A method is also disclosed that uses the above structure in order to perform the steps of using a folded memory as a way to increase the utilization rate of memory within the display controller.

Abstract translation: 提出了一种用于显示器的新的存储器控​​制器，例如包括一组第一驱动器（24）的类型的液晶显示器和一组第二驱动器（26），其一部分可以转换为所述 第一个司机（26b）。 还包括RAM存储器（62），其被构造为当在所述RAM存储器（62）处接收到主时钟信号时，在输入端接收数据并将所述数据输出到第一（24）和第二（26）驱动器的组。 存储器控制器包括被构造为产生所述主时钟信号的时钟信号发生器; 以及控制信号发生器电路，其被构造为产生用于所述RAM存储器（62）和所述第一（24）和第二（26）驱动器组的控制信号。 该存储器控制器的一个重要优点是它包括一组辅助寄存器（52），其被构造为在接收到从时钟周期之后临时存储从所述RAM存储器（62）接收到的所述数据的第一部分，并且所述一组辅助寄存器 （52），其被构造为在接收到所述主时钟信号之后将所述第一数据部分输出到所述转换成所述第一驱动器（26b）的所述第二驱动器的所述部分。 还公开了一种使用上述结构以便执行使用折叠存储器作为增加显示控制器内的存储器的利用率的方式的方法。

公开(公告)号：EP1104106A2

公开(公告)日：2001-05-30

申请号：EP00204130.9

申请日：2000-11-21

Applicant: STMicroelectronics S.r.l.

Inventor： Novelli, Aldo ,  Gariboldi, Roberto ,  Genova, Angelo ,  Filippo, Roberto

IPC: H03K17/06

CPC classification number: H03K17/04123 ,  H03K17/063

Abstract: A high side circuit is described which comprises at least one power device (1) having a first non drivable terminal (D) connected to a supply voltage (Vcc), at least one load (2) connected between a second non drivable terminal (S) of the power device (1) and ground, and driving circuitry (10). The driving circuitry (10) comprises suitable dimensioned transistors (M1, M2, M3) which are connected to each other and to a higher voltage (Vboot) than the supply voltage (Vcc) in order to control the turning on and the turning off of the power device (1) and to minimize the potential difference between the second non drivable terminal (S) and a drivable terminal (G) of the power device (1) during the turning off state to avoid the re-turning on of the same power device.

Abstract translation: 描述了一种高侧电路，其包括至少一个功率器件（1），其具有连接到电源电压（Vcc）的第一非驱动端子（D），连接在第二不可驱动端子（S）之间的至少一个负载（2） ）和驱动电路（10）。 驱动电路（10）包括彼此连接并具有比电源电压（Vcc）更高的电压（Vboot）的合适的尺寸尺寸的晶体管（M1，M2，M3），以便控制导通和断开 功率器件（1），并且在关闭状态期间将功率器件（1）的第二不可驱动端子（S）和可驱动端子（G）之间的电位差最小化以避免重新接通 电源设备。

公开(公告)号：EP0896268A1

公开(公告)日：1999-02-10

申请号：EP97830415.2

申请日：1997-08-07

Applicant: STMicroelectronics S.r.l.

Inventor： Genova, Angelo ,  Cantone, Giuseppe ,  Gariboldi, Roberto

IPC: G05F1/00 ,  G05F1/575 ,  H03K17/16

CPC classification number: H03K17/162 ,  G05F3/262

Abstract: An integrated device (105) for a switching system (100) comprises control means (110) for generating at least one switching control signal (Sh), reference means (120) for generating at least one reference quantity (Qref), means (110) for using the reference quantity (Qref), means (130) for storing the reference quantity (Qref), switch means (122) which, in a first operative condition, connect the reference means (120) to the using means (110) and to the storage means (130) in order to apply the reference quantity (Qref) thereto and, in a second operative condition, disconnect the reference means (120) from the using means (110) and connect the storage means (130) to the using means (110) in order to apply the stored reference quantity thereto, and filtering means (135) for keeping the switch means (122) in the second operative condition for a filtering period (Tf) in accordance with the switching of the control signal (Sh).

Abstract translation: 一种用于切换系统（100）的集成设备（105）包括用于产生至少一个切换控制信号（Sh）的控制装置（110），用于产生至少一个参考数量（Qref）的参考装置（120） ），用于存储参考数量（Qref）的装置（130），用于存储参考数量（Qref）的装置（130），在第一操作状态下将参考装置（120）连接到使用装置（110）的开关装置 并且向存储装置（130）提供参考数量（Qref），并且在第二操作条件下，使用参考装置（120）与使用装置（110）断开连接，并将存储装置（130）连接到 使用装置（110），以便将存储的参考数据应用于其中;以及滤波装置（135），用于根据控制的切换将开关装置（122）保持在第二操作状态中的过滤周期（Tf） 信号（Sh）。