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    Phase change memory device with overvoltage protection and method for protecting a phase change memory device against overvoltages
    11.
    发明公开
    Phase change memory device with overvoltage protection and method for protecting a phase change memory device against overvoltages 有权
    相变存储器以浪涌保护和保护方法，用于相变存储器与浪涌保护

    公开(公告)号：EP1538632A1

    公开(公告)日：2005-06-08

    申请号：EP03425728.7

    申请日：2003-11-12

    Applicant: STMicroelectronics S.r.l. ,  Universita' Degli Studi Di Pavia

    Inventor： Bedeschi, Ferdinando ,  Resta, Claudio ,  Torelli, Guido

    IPC: G11C11/34 ,  G11C7/12

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0059 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: A phase change memory device includes a plurality of PCM cells (3), arranged in rows and columns, PCM cells (3) arranged on the same column being connected to a same bit line (10); a plurality of first selectors (12), each coupled to a respective PCM cell (3); an addressing circuit (4, 5) for selectively addressing at least one of the bit lines (10), one of the first selectors (12), and the PCM cell (3) connected to the addressed bit line (10) and to the addressed first selector (12); and a regulated voltage supply circuit (7, 14, 15), selectively connectable to the addressed bit line (10), for supplying a bit line voltage (V BL ). The bit line voltage (V BL ) is correlated to a first control voltage (V EBA ) on the addressed first selector (12), coupled to the addressed PCM cell (3).

    Abstract translation: 一种相变存储器装置包括PCM单元的多个（3），以行和列布置，PCM单元（3）布置在相同的列被连接到相同的位线（10）; 第一选择器的多个（12），每个耦合到respectivement PCM单元（3）; 在用于选择性地寻址所述位线中的至少一个（10）中，第一选择器中的一个（12）和所述PCM单元寻址电路（4,5）（3）连接到所寻址的位线（10）和所述 寻址第一选择器（12）; 和经调节的电压供给电路（7，14，15）选择性地连接到用于供给位线电压（VBL）被寻址的位线（10）。 位线电压（VBL）被关联以在被寻址第一选择器（12），耦合到所寻址的PCM单元（3）的第一控制电压（VEBA）。

    Method for reading a multiple-level memory cell
    15.
    发明公开
    Method for reading a multiple-level memory cell 失效
    Verfahren zum Lesen einer Mehrbitspeicherzelle

    公开(公告)号：EP0945869A1

    公开(公告)日：1999-09-29

    申请号：EP98830188.3

    申请日：1998-03-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Maloberti, Franco ,  Oneto, Andrea ,  Torelli, Guido

    IPC: G11C11/00 ,  G11C11/56

    CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C11/5642

    Abstract: Method (200) for reading a multiple-level memory cell (C 12 ) capable of taking on three or more states which are represented by different values of a physical quantity (Icell) and each of which is associated with a corresponding logical value (LVcell), comprising the steps of setting (210) an actual physical quantity (Is 1 ) to a value correlated with the value of the physical quantity (Icell) corresponding to the state of the memory cell (C 12 ), and repeating (235), up to the complete determination of the logical value (LVcell) corresponding to the state of the memory cell (C 12 ), a cycle (215-235) comprising the steps of setting (227, 232) a component of the logical value (D i ) to a value which is a function of a range in which the actual physical quantity (Is i ) lies, determined by comparing (215, 220) the actual physical quantity (Is i ) with at least one reference physical quantity (Ir i ) having a predetermined value lying between a minimum value and a maximum value for the actual physical quantity (Is i ), and setting (237) the actual physical quantity for a possible next cycle (Is (i+1) ) to a relative value of the actual physical quantity (Is i ) with respect to the range in which it lies.

    Abstract translation: 用于读取能够承受三个或更多个状态的多级存储单元（C12）的方法（200），其由物理量（Icell）的不同值表示，并且每个与相应的逻辑值（LVcell）相关联， 包括以下步骤：将实际物理量（Is1）设置为与存储单元（C12）的状态对应的物理量（Icell）的值相关的值，并重复（235），直到 对与存储单元（C12）的状态相对应的逻辑值（LVcell）的完全确定，包括将逻辑值（Di）的分量设置为（227,232）的步骤的周期（215-235） 通过将实际物理量（Isi）与具有预定值之间的至少一个参考物理量（Iri）进行比较（215,220）来确定实际物理量（Isi）所在的范围的函数的值， 实际物理的最小值和最大值 数量（Isi）和将可能的下一个周期的实际物理量（Is（i + 1））设置为实际物理量（Isi）相对于其所在的范围的相对值。

    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device
    20.
    发明公开
    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device 有权
    在非易失性更通常高密度存储器和相关联的换能器为模拟/数字转换的方法

    公开(公告)号：EP1211812A3

    公开(公告)日：2003-02-12

    申请号：EP00127649.2

    申请日：2000-11-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

    IPC: H03M1/14 ,  G11C11/56

    CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

    Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg). The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB). The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.

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