VARIABLE RESISTANCE MEMORY DEVICE
    12.
    发明公开

    公开(公告)号:EP4160689A1

    公开(公告)日:2023-04-05

    申请号:EP22183728.9

    申请日:2022-07-08

    Abstract: A variable resistance memory device including a stack including insulating sheets (220) and conductive sheets (210), which are alternatingly stacked on a substrate, the stack including a vertical hole (VH) vertically penetrating therethrough, a bit line on the stack, a conductive pattern (320) electrically connected to the bit line and vertically extending in the vertical hole (VH), and a resistance varying layer (310) between the conductive pattern (320) and an inner side surface of the stack defining the vertical hole (VH) may be provided. The resistance varying layer (310) may include a first carbon nanotube (CNT1) electrically connected to the conductive sheets (210), and a second carbon nanotube (CNT2) electrically connected to the conductive pattern (320s).

    SEMICONDUCTOR MEMORY DEVICE
    13.
    发明公开

    公开(公告)号:EP3975258A1

    公开(公告)日:2022-03-30

    申请号:EP21180703.7

    申请日:2021-06-21

    Abstract: A semiconductor memory device includes a bit line (BL) extending in a first direction (Dl), a channel pattern (CP) on the bit line, the channel pattern including first and second vertical portions (VP1, VP2) facing each other and a horizontal portion (HP) connecting the first and second vertical portions, first and second word lines (WL1, WL2) provided on the horizontal portion and between the first and second vertical portions and extended in a second direction (D2) crossing the bit line, and a gate insulating pattern (Gox) provided between the first word line and the channel pattern and between the second word line and the channel pattern.

    SEMICONDUCTOR DEVICE
    15.
    发明公开

    公开(公告)号:EP4326028A1

    公开(公告)日:2024-02-21

    申请号:EP23162740.7

    申请日:2023-03-17

    Abstract: A semiconductor device includes first (CAR1) and second (CAR2) cell arrays. The first cell array includes a first gate electrode (GE1) that extends in a vertical direction (D2), a first channel pattern (CH1) on a side surface (GE1_S) of the first gate electrode, and a first bit line (BL1) electrically connected to the first channel pattern. The second cell array includes a second gate electrode (GE2) that extends in the vertical direction, a second channel pattern (CH2) on a side surface (GE2_S) of the second gate electrode, and a second bit line (BL2) electrically connected to the second channel pattern. A first bit line pad (BLP1) is electrically connected to the first bit line and a second bit line pad (BLP2) is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.

    SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME

    公开(公告)号:EP4307345A1

    公开(公告)日:2024-01-17

    申请号:EP23185512.3

    申请日:2023-07-14

    Abstract: The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device (1) includes a stack structure (ST) including interlayer insulating layers (33) and gate electrodes (75), a channel layer (52) disposed inside a hole (39) penetrating through the stack structure, a data storage layer (48) disposed between the stack structure and the channel layer, data storage patterns (45) disposed between the data storage layer and the gate electrodes, and dielectric layers (42) disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.

    SEMICONDUCTOR MEMORY DEVICE
    17.
    发明公开

    公开(公告)号:EP4287807A1

    公开(公告)日:2023-12-06

    申请号:EP23153463.7

    申请日:2023-01-26

    Abstract: A semiconductor memory device includes a first channel pattern and a second channel pattern stacked on a substrate, a word line disposed between the first and second channel patterns and that extends in a first direction parallel to a top surface of the substrate, a data storage pattern disposed between a top surface of the word line and the first channel pattern and between a bottom surface of the word line and the second channel pattern, a bit line that extends in a second direction perpendicular to the top surface of the substrate and that is connected to first end portions of the first and second channel patterns, and a source line that extends in the second direction and is connected to second end portions of the first and second channel patterns.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY CELL INCLUDING THE SAME

    公开(公告)号:EP4254512A1

    公开(公告)日:2023-10-04

    申请号:EP22217287.6

    申请日:2022-12-30

    Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern include oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.

    SEMICONDUCTOR DEVICE
    19.
    发明公开

    公开(公告)号:EP4148807A1

    公开(公告)日:2023-03-15

    申请号:EP22194350.9

    申请日:2022-09-07

    Abstract: A semiconductor device (100) is provided, and the semiconductor device includes: a channel (115); a gate structure (140) on the channel (115); a first source/drain (121) arranged at a first end of the channel (115) and including a metal; a first tunable band-gap layer (130) arranged between the channel (115) and the first source/drain (121) and having a band gap that changes according to stress; a first electrostrictive layer (150) between the gate structure (140) and the first tunable band-gap layer (130), the first electrostrictive layer (150) having a property of being deformed based on and upon application of an electric field; and a second source/drain (122) at a second end of the channel (115).

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