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公开(公告)号：US20210398925A1
公开(公告)日：2021-12-23
申请号：US17463559
申请日：2021-09-01
Applicant: Unimicron Technology Corp.
Inventor： John Hon-Shing Lau , Yu-Chi Shen , Tzyy-Jang Tseng , Chen-Hua Cheng , Pei-Wei Wang
Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
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公开(公告)号：US20210202407A1
公开(公告)日：2021-07-01
申请号：US16729488
申请日：2019-12-30
Applicant: Unimicron Technology Corp.
Inventor： John Hon-Shing Lau , Yu-Chi Shen , Tzyy-Jang Tseng , Chen-Hua Cheng , Pei-Wei Wang
Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
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公开(公告)号：US20210118839A1
公开(公告)日：2021-04-22
申请号：US16687557
申请日：2019-11-18
Applicant: Unimicron Technology Corp.
Inventor： Pu-Ju Lin , Cheng-Ta Ko , Ra-Min Tain , Tzyy-Jang Tseng
IPC: H01L23/00 , H01L23/538
Abstract: A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.
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公开(公告)号：US10957658B2
公开(公告)日：2021-03-23
申请号：US16866530
申请日：2020-05-04
Applicant: Unimicron Technology Corp.
Inventor： Pu-Ju Lin , Cheng-Ta Ko , Yu-Hua Chen , Tzyy-Jang Tseng , Ra-Min Tain
Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
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公开(公告)号：US10658282B2
公开(公告)日：2020-05-19
申请号：US16167540
申请日：2018-10-23
Applicant: Unimicron Technology Corp.
Inventor： Cheng-Ta Ko , Kai-Ming Yang , Yu-Hua Chen , Tzyy-Jang Tseng
IPC: H01L23/498
Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.
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Patent Agency Ranking
公开(公告)号：US20150305161A1
公开(公告)日：2015-10-22
申请号：US14255971
申请日：2014-04-18
Applicant: Unimicron Technology Corp.
Inventor： Tzyy-Jang Tseng , Wei-Ming Cheng
CPC classification number: H05K13/04 , H05K1/11 , H05K1/114 , H05K1/183 , H05K1/184 , H05K1/186 , H05K3/284 , H05K2201/09072 , H05K2201/10083 , H05K2201/10121 , H05K2201/10151
Abstract: An embedded component structure includes a wiring board, a component and an encapsulant. The wiring board has a front side, a reverse side opposite to the front side, an opening and an interconnection layer. The opening penetrates the wiring board and connects the front side and the reverse side of the wiring board. The interconnection layer is located on the front side of the wiring board and extends toward the opening. The component includes an active surface, a back side opposite to the active side, and a working area located on the active surface. The active surface is connected to the interconnection layer of the wiring board. The encapsulant is filled inside the opening and covers the component, which makes the working area of the component exposed. Besides, a method of the embedded component structure is also provided.
Abstract translation: 嵌入式组件结构包括布线板，部件和密封剂。 布线板具有前侧，与前侧相反的反面，开口和互连层。 开口穿过布线板并连接布线板的正面和背面。 互连层位于布线板的正面，朝向开口部延伸。 该部件包括活动表面，与活动侧相对的后侧以及位于活动表面上的工作区域。 有源表面连接到布线板的互连层。 密封剂填充在开口内部并覆盖部件，这使得部件的工作区域暴露。 此外，还提供了嵌入式组件结构的方法。
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公开(公告)号：US20130206467A1
公开(公告)日：2013-08-15
申请号：US13846875
申请日：2013-03-18
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen
CPC classification number: H05K3/06 , H05K1/0298 , H05K3/465 , H05K2201/0347 , Y10T29/49126 , Y10T29/49165
Abstract: A circuit board includes a circuit substrate, a first dielectric layer, a first conductive layer, a second conductive layer and a second dielectric layer. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer, and an intaglio pattern. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via. The second conductive layer is electrically connected to the first circuit layer via the first conductive layer. The second dielectric layer is disposed on the first dielectric layer and covers the second conductive layer and the second surface of the first dielectric layer.
Abstract translation: 电路板包括电路基板，第一介电层，第一导电层，第二导电层和第二介电层。 电路基板具有第一表面和第一电路层。 第一电介质层设置在电路基板上并覆盖第一表面和第一电路层。 第一电介质层具有第二表面，至少从第二表面延伸到第一电路层的盲孔以及凹版图案。 第一导电层设置在盲孔中。 第二导电层设置在凹版图案和盲孔中。 第二导电层经由第一导电层电连接到第一电路层。 第二电介质层设置在第一电介质层上并覆盖第二导电层和第一介电层的第二表面。
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公开(公告)号：US20250125298A1
公开(公告)日：2025-04-17
申请号：US18486172
申请日：2023-10-13
Applicant: Unimicron Technology Corp.
Inventor： John Hon-Shing Lau , Tzyy-Jang Tseng
IPC: H01L23/00 , H01L23/538 , H01L25/00 , H01L25/065 , H01L25/10
Abstract: A chip package structure includes a first chip, a second chip, a plurality of first hybrid bonding pads, a first insulating layer, a first patterned conductive layer, a second patterned conductive layer, and a plurality of first conductive via structures and second conductive via The first chip is electrically connected to the second chip through a plurality of first 5 structures. through silicon vias. The first chip is bonded onto the second chip through the first hybrid bonding pads. The first insulating layer covers the first and the second chips. The first and the second patterned conductive layers are respectively disposed on a first upper surface and a first lower surface of the first insulating layer. The first conductive via structures are electrically connected to the first and the second patterned conductive layers. The second conductive via structures are electrically connected to the first chip and the first patterned conductive layer.
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公开(公告)号：US11991824B2
公开(公告)日：2024-05-21
申请号：US17448893
申请日：2021-09-26
Applicant: Unimicron Technology Corp.
Inventor： Tzyy-Jang Tseng , Cheng-Ta Ko , Pu-Ju Lin , Chi-Hai Kuo , Shao-Chien Lee , Ming-Ru Chen , Cheng-Chung Lo
IPC: H05K1/02 , G02F1/1333 , G02F1/1368 , H05K1/03 , H05K1/11 , H05K3/00 , H10K59/12 , H10K59/123 , H10K59/124 , H10K59/131
CPC classification number: H05K1/115 , H05K1/0306 , H05K3/0067 , H05K3/0094
Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.
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公开(公告)号：US11837591B2
公开(公告)日：2023-12-05
申请号：US17714121
申请日：2022-04-05
Applicant: Unimicron Technology Corp.
Inventor： Ming-Ru Chen , Tzyy-Jang Tseng , Cheng-Chung Lo
CPC classification number: H01L25/167 , H01L33/62 , H01L33/56 , H01L2933/0066
Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
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