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11.发明申请METHODS AND STRUCTURES FOR THIN-FILM ENCAPSULATION AND CO-INTEGRATION OF SAME WITH MICROELECTRONIC DEVICES AND MICROELECTROMECHANICAL SYSTEMS (MEMS) 审中-公开微电子器件和微电子系统（MEMS）的薄膜封装和共同组合的方法和结构公开(公告)号：US20160362295A1
公开(公告)日：2016-12-15
申请号：US15246278
申请日：2016-08-24
Inventor： Emmanuel P. Quevy , Jeremy R. Hui , Carrie Wing-Zin Low , Mehrnaz Motiee
CPC classification number: B81C1/00246 , B81B3/0021 , B81B7/007 , B81B7/0077 , B81B7/008 , B81B2201/0214 , B81B2201/0235 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C1/00269 , B81C1/00285 , B81C1/00333 , B81C1/0038 , B81C2201/0105 , B81C2201/056 , B81C2203/0118 , B81C2203/0136 , B81C2203/0172 , B81C2203/019 , B81C2203/0735 , G01N27/223 , G01N27/227 , H05K999/99
Abstract: Methods and structures that may be implemented in one example to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) such as sensors and actuators. For example, structures having varying characteristics may be fabricated using the same basic process flow by selecting among different process options or modules for use with the basic process flow in order to create the desired structure/s. Various process flow sequences as well as a variety of device design structures may be advantageously enabled by the various disclosed process flow sequences.
Abstract translation: 可以在一个示例中实现的方法和结构，以共同整合用于薄膜封装和形成微电子器件和微机电系统（MEMS）例如传感器和致动器的过程。 例如，可以使用相同的基本工艺流程来制造具有不同特性的结构，通过选择与基本工艺流程一起使用的不同工艺选项或模块以便创建所需的结构。 可以通过各种公开的处理流程序列有利地实现各种处理流程序列以及各种设备设计结构。
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公开(公告)号：JP2016531006A
公开(公告)日：2016-10-06
申请号：JP2016522377
申请日：2014-06-11
Applicant: ソイテックSoitec
Inventor： マリアム サダカ， , マリアム サダカ， , ルドヴィック エスカルノー， , ルドヴィック エスカルノー，
CPC classification number: B81C1/00047 , B81B1/002 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C2201/0105 , B81C2201/014 , B81C2201/0192
Abstract: 微小電気機械システム(MEMS)トランスデューサの形成において使用することができる、1つ又は複数のキャビティ(106)を備える半導体構造を形成する方法は、第1の基板(100)に1つ又は複数のキャビティを形成するステップと、1つ又は複数のキャビティ内部に犠牲材料(110)を設けるステップと、第1の基板の表面上に第2の基板(120)を接合するステップと、第1の基板の一部を貫いて犠牲材料まで1つ又は複数の開口(140)を形成するステップと、1つ又は複数のキャビティ内部から犠牲材料を除去するステップと、を含む。構造及びデバイスがそのような方法を使用して作製される。【選択図】図11
Abstract translation: 可以在微机电系统的形成中使用（MEMS）换能器，从而形成半导体结构，包括一个腔体（106）的一个或多个方法，在第一基板的一个或多个腔体（100） 形成以下步骤：一个或多个腔中提供一个牺牲材料（110），并且所述第一基板的表面上接合的第二基板（120），第一基板 并通过部形成一个或多个开口（140）到所述牺牲材料，并从内部空腔除去所述一种或多种牺牲材料的。 的结构和设备使用这样的方法制造。 .The 11
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公开(公告)号：WO2016057220A1
公开(公告)日：2016-04-14
申请号：PCT/US2015/051656
申请日：2015-09-23
Applicant: PIXTRONIX, INC.
Inventor： VILLARREAL, Javier , BROSNIHAN, Timothy , HO, Chin-Yuan , LIN, Hung-Chien
IPC: G02B26/02
CPC classification number: B81C1/00523 , B81B3/0029 , B81B7/02 , B81B2201/045 , B81B2203/0307 , B81C1/0019 , B81C1/00412 , B81C2201/0105 , B81C2201/0159 , G02B26/02 , G06T1/20
Abstract: This disclosure provides systems, methods and apparatus including processes that use two layers of resist, with a layer of etch stop material in between. The two layers of resist may be etched in separate processes to form devices having vias with sidewalls that extend through both layers of resist
Abstract translation: 本公开提供了包括使用两层抗蚀剂的工艺的系统，方法和设备，其间具有一层蚀刻停止材料。 可以在单独的工艺中蚀刻两层抗蚀剂，以形成具有延伸穿过两层抗蚀剂的侧壁的通路的器件
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公开(公告)号：WO2011120773A1
公开(公告)日：2011-10-06
申请号：PCT/EP2011/053573
申请日：2011-03-10
Inventor： SCHOEN, Christian , WAGENER, Michael
IPC: B01L3/00
CPC classification number: B01J4/001 , B01L3/502707 , B01L3/502738 , B01L3/502746 , B01L2200/0621 , B01L2200/10 , B01L2300/0636 , B01L2300/0681 , B01L2300/0816 , B01L2300/0822 , B01L2300/0864 , B01L2300/0887 , B01L2300/161 , B01L2400/0406 , B01L2400/0688 , B01L2400/088 , B81C1/00047 , B81C1/00063 , B81C2201/0105 , B81C2201/0143 , B81C2201/0156 , Y10T137/85938
Abstract: Die Erfindung betrifft ein Bauteil (4) eines Biosensors, mit wenigstens einer ersten Einrichtung (6) zur Aufnahme einer Probenflüssigkeit, wobei die Einrichtung (6) über einen Verteilerkanal (7) mit weiteren Aufnahmeeinrichtungen (8 bis 11) verbunden ist, in die jeweils ein vom Verteilerkanal (7) abzweigender Zulaufkanal (71, 72, 73, 74) mündet und die Zulaufkanäle (71, 72, 73, 74) in Strömungsrichtung (S) der durch den Verteilerkanal (7) weitergeleiteten Probenflüssigkeit aufeinander folgend angeordnet sind. Erfindungsgemäß ist vorgesehen, dass im Verteilerkanal (7) jeweils zwischen zwei in Strömungsrichtung (S) unmittelbar aufeinander folgenden Zulaufkanälen (71, 72; 72, 73; 73, 74) wenigstens ein Bereich (K) zum zumindest zeitweisen Verlangsamen oder Stoppen des kapillaren Flusses der Probenflüssigkeit eingebracht ist. Hierdurch ist es möglich, den kapillaren Fluss der Probenflüssigkeit so zu steuern, dass mit dem zur Verfügung stehenden Volumenstrom an Probenflüssigkeit immer nur jeweils eine Aufnahmeeinrichtung (8, 9, 10, 11) befüllt wird, bevor die nächste befüllt wird und eine quasi gleichzeitige Befüllung der Aufnahmeeinrichtungen (8, 9, 10, 11) verhindert wird. Dies führt zu einer schnellen und vollständigen Befüllung der jeweiligen Aufnahmeeinrichtung (8, 9, 10, 11). Des Weiteren wird ein Verfahren vorgestellt, mit dem auf einfache Weise die Bereiche (K) in den Verteilerkanal (7) eingebracht werden können.
Abstract translation: 本发明涉及的成分（4），其具有的生物传感器中的至少一个第一装置（6），用于接收样品液，其中，所述装置（6）通过分配器通道（7）与另外的接收装置（8〜11）连接，在各 一个从所述入口管道（71，72，73，74）分支出分配通道（7）打开，并且所述入口通道（71，72，73，74）在由转发（7）的样品液体中的分配通道的流动方向（S）被连续布置。 根据本发明，它提供了在流动（S）直接连续流入通道的方向上的每两个之间的分配通道（7）（71，72; 72，73; 73，74）的至少一部分（K）用于至少暂时减缓或毛细流动的停止 样品液体被引入。 这使得有可能以控制样品液体的毛细管流动，使得填充有样品液体的可用流永远只有一个记录装置（8，9，10，11）之前的下一个填充和一个准同步灌装 记录装置（8，9，10，11）被防止。 这导致相应的接收装置（8，9，10，11）的快速和完全的填充。 此外，提出了一种方法，通过它以简单的方式（K）的区域到所述分配通道（7）可被引入。
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公开(公告)号：US20240359973A1
公开(公告)日：2024-10-31
申请号：US18028567
申请日：2022-04-27
Inventor： Yingli SHI , Chao ZHOU , Yanzhao LI
CPC classification number: B81B7/02 , B81C1/00142 , H01H59/0009 , H01P1/122 , B81B2201/01 , B81B2203/0109 , B81B2203/0323 , B81B2203/0353 , B81C2201/0105
Abstract: A MEMS switch, a preparation method thereof, and an electronic apparatus. The MEMS switch includes: a substrate, a coplanar waveguide line structure disposed on a side of the substrate, an isolation structure disposed on a side of the coplanar waveguide line structure away from the substrate, a film bridge disposed on a side of the isolation structure away from the substrate. The coplanar waveguide line structure includes a first wire, a first DC bias line, a second wire, a second DC bias line and a third wire arranged at intervals sequentially. The second wire is one of an RF signal transmission line and a ground line, the first wire and the third wire are the other of the RF signal transmission line and the ground line. The film bridge is crossed between the first wire and third wire, and is connected with the first wire and the third wire respectively.
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Patent Agency Ranking
16.发明授权公开(公告)号：US12037239B2
公开(公告)日：2024-07-16
申请号：US17206116
申请日：2021-03-18
Inventor： You Qian , Humberto Campanella-Pineda , Rakesh Kumar
IPC: B81C1/00 , B06B1/06 , B81B3/00 , H10N30/06 , H10N30/074 , H10N30/093 , H10N30/87 , H10N39/00 , H10N30/853 , H10N30/88
CPC classification number: B81C1/00246 , B06B1/06 , B81B3/0021 , H10N30/06 , H10N30/074 , H10N30/875 , H10N39/00 , B81B2201/0271 , B81B2201/032 , B81B2207/015 , B81B2207/096 , B81B2207/115 , B81C2201/0105 , B81C2203/0735 , B81C2203/0771 , H10N30/093 , H10N30/853 , H10N30/883
Abstract: A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.
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公开(公告)号：US20240199413A1
公开(公告)日：2024-06-20
申请号：US18594647
申请日：2024-03-04
Applicant: X-Celprint Limited
Inventor： Pierluigi Rubino
IPC: B81C1/00
CPC classification number: B81C1/00039 , B81C1/00523 , B81C1/00555 , B81C2201/0105 , B81C2201/013
Abstract: A micro-device structure comprises a source substrate having a sacrificial layer comprising a sacrificial portion adjacent to an anchor portion, a micro-device disposed completely over the sacrificial portion, the micro-device having a top side opposite the sacrificial portion and a bottom side adjacent to the sacrificial portion and comprising an etch hole that extends through the micro-device from the top side to the bottom side, and a tether that physically connects the micro-device to the anchor portion. A micro-device structure comprises a micro-device disposed on a target substrate. Micro-devices can be 10 any one or more of an antenna, a micro-heater, a power device, a MEMs device, and a micro-fluidic reservoir.
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公开(公告)号：US20240182292A1
公开(公告)日：2024-06-06
申请号：US18437345
申请日：2024-02-09
Inventor： Ting-Jung Chen
CPC classification number: B81B3/0072 , B81C1/00666 , H04N23/54 , H04N23/687 , B81B2203/0118 , B81B2203/019 , B81B2203/0307 , B81C2201/0105 , B81C2201/0178 , G02B7/021
Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a MEMS (microelectromechanical systems) actuator. The MEMS actuator has an anchor. A proof mass continuously wraps around the anchor in a closed loop. One or more curved cantilevers are coupled between the proof mass and a frame. The frame wraps around the proof mass. The one or more curved cantilevers include curved outer surfaces arranged directly between a sidewall of the frame and a sidewall of the proof mass, as viewed in a top-view.
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公开(公告)号：US20240051819A1
公开(公告)日：2024-02-15
申请号：US18073472
申请日：2022-12-01
Inventor： Ping-He Chang , Kahkeen Lai
IPC: B81C1/00
CPC classification number: B81C1/00476 , B81C2201/0105 , B81C2201/0132 , B81C2201/0133 , B81C2203/0172
Abstract: A method for manufacturing a MEMS device and the MEMS device are provided. The method includes: depositing a film on at least a part of a surface of a sacrificial layer, defining at least one through hole in the thin film by machining, removing at least a part of a material covered by the thin film in the sacrificial layer, discharging the part of the material removed from the sacrificial layer from the at least one through hole to define a cavity in the sacrificial layer, and depositing a sealing layer on a surface of the thin film facing away from the sacrificial layer to seal the at least one through hole. Compared with the manufacturing method in the related art, the manufacturing method of the disclosure only requires to deposit one layer of thin film, shorten the production period, and has reliable on-site sealing capability.
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20.发明公开公开(公告)号：US20240017990A1
公开(公告)日：2024-01-18
申请号：US18301162
申请日：2023-04-14
Applicant: Microfabrica Inc.
Inventor： Duy P. Le , Rulon J. Larsen , Jeffrey A. Thompson , Uri Frodis , Dale S. McPherson , Kleun Kim , Mahmood Samiee , Nina C. Levy , Dennis R. Smalley
IPC: B81C99/00
CPC classification number: B81C99/003 , B81C99/004 , B81C2201/0105 , B81C2201/013
Abstract: Electronic test probes formed in a batch have a plurality of multi-material layers wherein at least one of the materials is a sacrificial material and at least one other material is a structural material. Successfully formed or good test probes are separated from unsuccessfully formed or bad test probes
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