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    EPI-POLY ETCH STOP FOR OUT OF PLANE SPACER DEFINED ELECTRODE
    11.
    发明申请
    EPI-POLY ETCH STOP FOR OUT OF PLANE SPACER DEFINED ELECTRODE 审中-公开
    EPI-POLY ETCH STOP FOR PLANE SPACER定义电极

    公开(公告)号：WO2014150091A1

    公开(公告)日：2014-09-25

    申请号：PCT/US2014/022186

    申请日：2014-03-08

    Applicant: ROBERT BOSCH GMBH ,  GRAHAM, Andrew ,  YAMA, Gary ,  O'BRIEN, Gary

    Inventor： GRAHAM, Andrew ,  YAMA, Gary ,  O'BRIEN, Gary

    IPC: H01L21/28

    CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  B81B2203/04 ,  B81B2203/053 ,  B81C1/00095 ,  B81C1/00166 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/0177 ,  B81C2203/0136

    Abstract: In one embodiment, a method of forming an out-of-plane electrode includes forming an oxide layer above an upper surface of a device layer, etching an etch stop perimeter defining trench extending through the oxide layer, forming a first cap layer portion on an upper surface of the oxide layer and within the etch stop perimeter defining trench, etching a first electrode perimeter defining trench extending through the first cap layer portion and stopping at the oxide layer, depositing a first material portion within the first electrode perimeter defining trench, depositing a second cap layer portion above the deposited first material portion, and vapor releasing a portion of the oxide layer with the etch stop portion providing a lateral etch stop.

    Abstract translation: 在一个实施例中，形成平面外电极的方法包括在器件层的上表面上形成氧化物层，蚀刻限定延伸穿过氧化物层的沟槽的蚀刻停止周界，在第一帽层部分上形成 氧化物层的上表面，并且在蚀刻停止周界内限定沟槽，蚀刻延伸穿过第一盖层部分并停止在氧化物层处的第一电极周界，限定沟槽，在第一电极周界限定沟槽内沉积第一材料部分，沉积 在沉积的第一材料部分上方的第二盖层部分，以及用蚀刻停止部分提供横向蚀刻停止物来释放一部分氧化物层的蒸气。

    METHOD OF IMPROVING THIN-FILM ENCAPSULATION FOR AN ELECTROMECHANICAL SYSTEMS ASSEMBLY
    13.
    发明申请
    METHOD OF IMPROVING THIN-FILM ENCAPSULATION FOR AN ELECTROMECHANICAL SYSTEMS ASSEMBLY 审中-公开
    改进电磁系统组装薄膜封装的方法

    公开(公告)号：WO2013066773A1

    公开(公告)日：2013-05-10

    申请号：PCT/US2012/062287

    申请日：2012-10-26

    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.

    Inventor： HE, Rihui ,  LONDERGAN, Ana Rangelova ,  GOUSEV, Evgeni Petrovich

    IPC: B81C1/00

    CPC classification number: B81C1/00333 ,  B81C2201/0177 ,  B81C2201/0181 ,  B81C2203/0145

    Abstract: This disclosure provides systems, methods, and apparatus for fabricating electromechanical systems devices. In one aspect, a method of sealing an electromechanical systems device includes etching a sacrificial layer. The sacrificial layer is formed between a surface of a substrate and a shell layer and is etched through etch holes in the shell layer formed over the electromechanical systems device. The etch holes in the shell layer have a diameter greater than about one micron. The shell layer is then treated. A seal layer is deposited on the treated shell layer. The seal layer hermetically seals the electromechanical systems device.

    Abstract translation: 本公开提供了用于制造机电系统装置的系统，方法和装置。 一方面，密封机电系统装置的方法包括蚀刻牺牲层。 牺牲层形成在基底的表面和壳层之间，并通过在机电系统器件上形成的壳层中的蚀刻孔进行蚀刻。 壳层中的蚀刻孔的直径大于约1微米。 然后对壳层进行处理。 密封层沉积在经处理的壳层上。 密封层密封机电系统装置。

    SEMICONDUCTOR STRUCTURE
    14.
    发明申请
    SEMICONDUCTOR STRUCTURE 审中-公开
    半导体结构

    公开(公告)号：WO2012153112A2

    公开(公告)日：2012-11-15

    申请号：PCT/GB2012/050980

    申请日：2012-05-04

    Applicant: THE UNIVERSITY OF WARWICK ,  SHAH, Vishal Ajit ,  MYRONOV, Maksym

    Inventor： SHAH, Vishal Ajit ,  MYRONOV, Maksym

    IPC: B81C1/00

    CPC classification number: B81C1/00158 ,  B81C2201/017 ,  B81C2201/0177 ,  H01L21/3081

    Abstract: A semiconductor structure comprises a frame (24) provided by a monocrystalline substrate comprising a first semiconductor material and having a window passing through the substrate between first and second opposite surfaces of the substrate; and a monocrystalline membrane (4) over the window provided by a layer supported directly on the first surface of the substrate, the membrane comprising a second, different semiconductor material which is under tensile strain.

    Abstract translation: 半导体结构包括由单晶衬底提供的框架（24），所述单晶衬底包括第一半导体材料并且具有穿过所述衬底的窗口，所述窗口在所述衬底的第一和第二相对表面之间; 以及由直接支撑在所述基板的第一表面上的层提供的窗口上的单晶膜（4），所述膜包括处于拉伸应变的第二不同的半导体材料。

    VERFAHREN ZUR HERSTELLUNG VON MEMS-STRUKTUREN
    15.
    发明申请
    VERFAHREN ZUR HERSTELLUNG VON MEMS-STRUKTUREN 审中-公开
    用于生产MEMS结构

    公开(公告)号：WO2008006641A1

    公开(公告)日：2008-01-17

    申请号：PCT/EP2007/054988

    申请日：2007-05-23

    Applicant: ROBERT BOSCH GMBH ,  SCHEURLE, Andreas

    Inventor： SCHEURLE, Andreas

    IPC: B81C1/00

    CPC classification number: B81C1/00714 ,  B81C2201/0109 ,  B81C2201/0177

    Abstract: Die Erfindung betrifft ein Verfahren zur Herstellung von MEMS-Strukturen mit mindestens einer Funktionsschicht aus Silizium, die Strukturen enthält, die durch Entfernen einer Opferschicht freigestellt werden, wobei mindestens eine Opferschicht und mindestens eine Funktionsschicht so abgeschieden werden, dass sie einkristallin aufwachsen, und die Opferschicht aus einer Silizium-Germanium-Mischschicht besteht.

    Abstract translation: 本发明涉及一种用于具有通过去除牺牲层分离含有硅结构中的至少一个功能层的制造MEMS结构，其中至少一个牺牲层和至少一个功能层被沉积以使它们生长单晶，以及牺牲层 由硅 - 锗混合层。

    METHOD OF FORMING SEMICONDUCTOR DEVICES THROUGH EPITAXY
    16.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICES THROUGH EPITAXY 审中-公开
    通过外延形成半导体器件的方法

    公开(公告)号：WO2004060792A3

    公开(公告)日：2004-10-21

    申请号：PCT/US0333630

    申请日：2003-10-23

    Applicant: FREESCALE SEMICONDUCTOR INC

    Inventor： GOGOI BISHNU

    IPC: B81B3/00 ,  B81C1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/36

    CPC classification number: B81B3/001 ,  B81C2201/0109 ,  B81C2201/0177

    Abstract: A method for creating a semiconductor structure is provided. In accordance with the method, a semiconductor substrate (101) is provided over which is disposed a sacrificial layer (103), and which has a thin single crystal semiconductor layer (105) disposed over the sacrificial layer (103). An opening (107) is then created which extends through the semiconductor layer (105) and into the sacrificial layer (103). The semiconductor layer (105) is then epitaxially grown to a suitable device thickness, thereby resulting in a device layer. The semiconductor layer is grown such that the resulting device layer extends over the opening (107), and such that the surface of the portion of the device layer extending over the opening is single crystal silicon.

    Abstract translation: 提供了一种用于创建半导体结构的方法。 根据该方法，提供半导体衬底（101），其上设置有牺牲层（103），并且具有设置在牺牲层（103）上的薄的单晶半导体层（105）。 然后形成延伸穿过半导体层（105）并进入牺牲层（103）的开口（107）。 然后将半导体层（105）外延生长至合适的器件厚度，由此得到器件层。 生长半导体层使得所得器件层在开口（107）上延伸，并且使得在开口上方延伸的器件层的部分的表面是单晶硅。

    METHOD FOR FABRICATING SUSPENDED MEMS STRUCTURES
    17.
    发明申请
    METHOD FOR FABRICATING SUSPENDED MEMS STRUCTURES 审中-公开
    制造悬挂MEMS结构的方法

    公开(公告)号：WO2016167853A1

    公开(公告)日：2016-10-20

    申请号：PCT/US2016/014223

    申请日：2016-01-21

    Applicant: THE GOVERNMENT OF THE UNITED STATES OF AMERICA, as represented by THE SECRETARY OF THE NAVY ,  MEYER, David, J. ,  DOWNEY, Brian, P.

    Inventor： MEYER, David, J. ,  DOWNEY, Brian, P.

    IPC: B81C1/00 ,  B81B7/00 ,  B81B7/02 ,  H01L27/04

    CPC classification number: B81C1/00539 ,  B81C1/00936 ,  B81C2201/0107 ,  B81C2201/0132 ,  B81C2201/0143 ,  B81C2201/0159 ,  B81C2201/0177

    Abstract: A process for fabricating a suspended microelectromechanical system (MEMS) structure comprising epitaxial semiconductor functional layers that are partially or completely suspended over a substrate. A sacrificial release layer and a functional device layer are formed on a substrate. The functional device layer is etched to form windows in the functional device layer defining an outline of a suspended MEMS device to be formed from the functional device layer. The sacrificial release layer is then etched with a selective release etchant to remove the sacrificial release layer underneath the functional layer in the area defined by the windows to form the suspended MEMS structure.

    Abstract translation: 一种用于制造包括部分地或完全地悬置在衬底上的外延半导体功能层的悬置微机电系统（MEMS）结构的工艺。 牺牲释放层和功能器件层形成在衬底上。 对功能器件层进行蚀刻以在功能器件层中形成窗口，从而界定将从功能器件层形成的悬置MEMS器件的轮廓。 然后用选择性释放蚀刻剂对牺牲释放层进行蚀刻，以去除由窗口限定的区域中的功能层下方的牺牲释放层，以形成悬浮的MEMS结构。

    MICROMECHANICAL DEVICE AND METHOD OF DESIGNING THEREOF
    18.
    发明申请
    MICROMECHANICAL DEVICE AND METHOD OF DESIGNING THEREOF 审中-公开
    微机电设备及其设计方法

    公开(公告)号：WO2012156585A1

    公开(公告)日：2012-11-22

    申请号：PCT/FI2012/050456

    申请日：2012-05-11

    Applicant: TEKNOLOGIAN TUTKIMUSKESKUS VTT ,  PRUNNILA, Mika ,  JAAKKOLA, Antti ,  PENSALA, Tuomas

    Inventor： PRUNNILA, Mika ,  JAAKKOLA, Antti ,  PENSALA, Tuomas

    IPC: H03H9/02 ,  H03H9/24 ,  B81B3/00

    CPC classification number: B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0271 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0177 ,  G06F17/5045 ,  H03H9/02448 ,  H03H9/2447 ,  H03H2009/2442

    Abstract: The invention relates to a micromechanical device comprising a semiconductor element capable of deflecting or resonating and comprising at least two regions having different material properties and drive or sense means functionally coupled to said semiconductor element. According to the invention, at least one of said regions comprises one or more n-type doping agents, and the relative volumes, doping concentrations, doping agents and/or crystal orientations of the regions being configured so that the temperature sensitivities of the generalized stiffness are opposite in sign at least at one temperature for the regions, and the overall temperature drift of the generalized stiffness of the semiconductor element is 50 ppm or less on a temperature range of 100°C. The device can be a resonator. Also a method of designing the device is disclosed.

    Abstract translation: 本发明涉及一种微机械装置，其包括能够偏转或谐振并且包括具有不同材料特性的至少两个区域的半导体元件和功能性耦合到所述半导体元件的驱动或感测装置。 根据本发明，所述区域中的至少一个包括一种或多种n型掺杂剂，并且所述区域的相对体积，掺杂浓度，掺杂剂和/或晶体取向被构造成使得广义刚度的温度敏感度 至少在区域的一个温度下符号相反，半导体元件的整体刚度的总体温度漂移在100℃的温度范围内为50ppm以下。 该器件可以是谐振器。 还公开了一种设计该设备的方法。

    MEMS DEVICE AND METHOD OF MANUFACTURING MEMS DEVICE
    20.
    发明公开
    MEMS DEVICE AND METHOD OF MANUFACTURING MEMS DEVICE 审中-公开

    公开(公告)号：US20240017989A1

    公开(公告)日：2024-01-18

    申请号：US18348664

    申请日：2023-07-07

    Applicant: ROHM CO., LTD.

    Inventor： Martin Wilfried HELLER

    IPC: B81C1/00 ,  B81B7/02

    CPC classification number: B81C1/00166 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81B2203/033 ,  B81B2203/04 ,  B81C2201/0132 ,  B81C2201/0177 ,  B81C2201/019 ,  B81C2201/0178

    Abstract: A MEMS device includes a substrate which has a first main surface and a second main surface facing the first main surface, and in which a silicon substrate, a silicon carbide layer having conductivity, and a silicon layer are sequentially stacked from a second main surface side toward a first main surface side, a cavity recessed over the silicon layer, the silicon carbide layer, and the silicon substrate from the first main surface of the substrate to the second main surface side of the substrate, a MEMS electrode which is arranged in the cavity, is composed of the silicon layer and the silicon carbide layer, and is spaced apart from a bottom surface of the cavity to the first main surface side, and an isolation joint which divides the MEMS electrode in a plan view and mechanically connects and electrically isolates both sides of the divided MEMS electrode.

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