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    A METHOD AND APPARATUS FOR DETECTING ERRORS IN DATA OUTPUT FROM MEMORY AND A DEVICE FAILURE IN THE MEMORY
    12.
    发明申请
    A METHOD AND APPARATUS FOR DETECTING ERRORS IN DATA OUTPUT FROM MEMORY AND A DEVICE FAILURE IN THE MEMORY 审中-公开
    用于检测存储器中的数据输出中的错误和存储器中的器件故障的方法和装置

    公开(公告)号：WO0038064A9

    公开(公告)日：2000-12-07

    申请号：PCT/US9930170

    申请日：1999-12-22

    Applicant: INTEL CORP

    Inventor： HOLMAN THOMAS J ,  MACWILLIAMS PETER D

    IPC: G06F11/10

    CPC classification number: G06F11/1028 ,  G06F11/1036

    Abstract: A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.

    Abstract translation: 一种用于检测从存储器输出的数据中的错误和存储器中的设备故障的方法和装置。 在本发明中，基于要输入到存储器的数据生成校验码。 检查码在等于零​​时有效。 响应于写命令，校验码被反转并作为代码字与数据一起输入存储器。 响应于读取命令，从存储器输出码字。 从存储器输出的码字指示存储器中的设备是否失败。 包括在从存储器输出的码字中的反转检查码被重新反转。 指示基于包括校验码的数据和码字来生成包括在从存储器输出的码字中包括的数据是否包含错误的信息。

    A METHOD AND APPARATUS FOR DETECTING ERRORS IN DATA OUTPUT FROM MEMORY AND A DEVICE FAILURE IN THE MEMORY
    13.
    发明申请
    A METHOD AND APPARATUS FOR DETECTING ERRORS IN DATA OUTPUT FROM MEMORY AND A DEVICE FAILURE IN THE MEMORY 审中-公开
    用于检测来自存储器和存储器设备故障的数据输出信号中的错误的方法和设备故障

    公开(公告)号：WO00038064A1

    公开(公告)日：2000-06-29

    申请号：PCT/US1999/030170

    申请日：1999-12-22

    IPC: G06F11/10

    CPC classification number: G06F11/1028 ,  G06F11/1036

    Abstract: A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.

    Abstract translation: 一种用于检测来自存储器的数据输出信号中的错误以及存储器设备故障的方法和设备。 在本发明中，在数据库上产生验证码以引入存储器。 验证码在等于零​​时有效。 响应于写入命令，验证码被反转并且将数据作为码字输入到存储器中。 响应于读取命令，从存储器提取编码的字。 从存储器提取的码字指示存储器设备是否发生故障。 包含在从存储器提取的码字中的反相验证码再次反转。 基于包含验证码的数据和码字产生指示包括在从存储器提取的码字中包括的数据是否包括错误的信息。

    A METHOD AND APPARATUS FOR DETECTING ERRORS IN DATA OUTPUT FROM MEMORY AND A DEVICE FAILURE IN THE MEMORY
    15.
    发明公开
    A METHOD AND APPARATUS FOR DETECTING ERRORS IN DATA OUTPUT FROM MEMORY AND A DEVICE FAILURE IN THE MEMORY 有权
    方法和设备内存数据错误检测和存储器模块故障检测

    公开(公告)号：EP1141830A1

    公开(公告)日：2001-10-10

    申请号：EP99966405.5

    申请日：1999-12-22

    Applicant: INTEL CORPORATION

    Inventor： HOLMAN, Thomas, J. ,  MACWILLIAMS, Peter, D.

    IPC: G06F11/10

    CPC classification number: G06F11/1028 ,  G06F11/1036

    Abstract: A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.

    Self-checking microprogram control unit with on-line error detection capability, in MOS technology
    17.
    发明公开
    Self-checking microprogram control unit with on-line error detection capability, in MOS technology 失效
    SelbstprüfendesMikroprogramm-Steuerwerk在MOS-Technologie mit On-line-Fehlererkennungsfähigkeit。

    公开(公告)号：EP0199120A2

    公开(公告)日：1986-10-29

    申请号：EP86104011.1

    申请日：1986-03-24

    Applicant: CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A.

    Inventor： Melgara, Marcello ,  Paolini, Maurizio ,  Turolla, Maura

    IPC: G06F11/00

    CPC classification number: G06F11/1008 ,  G06F9/226 ,  G06F11/00 ,  G06F11/0763 ,  G06F11/10 ,  G06F11/1036 ,  G06F11/1076 ,  G06F11/16 ,  G06F11/28 ,  H03M13/51

    Abstract: The control unit detects the errors concurrently with normal microinstruction execution through suitable internal checking circuits and a determined microinstruction allocation in the memory.
    Microinstructions comprise additional field (CS, FS) carrying the encoding, in modified Berger code, of the allocation address of the microinstruction itself and of the following one; the microinstructions of destination itself and of the following one; the microinstructions of destination of conditional jumps are allocated so that their codes are related to each other by simple logic relationships which are then reproduced by an internal circuit (CSM); the two fields, the one of the next microinstruction being duly delayed, are then compared and possible differences detect unidirectional and incorrect sequencing errors.
    The other errors are detected through particular implementations of some internal circuits (STK1, INC1) and duplication of others (RCT, SEL).

    Abstract translation: 控制单元通过适当的内部检查电路和存储器中确定的微指令分配来检测与正常微指令执行同时发生的错误。 微指令包括附加字段（CS，FS），其以修改的Berger代码携带微指令本身和随后的分配地址的编码; 目的地本身和以下的微指令; 分配条件跳转的目的地的微指令，使得它们的代码通过简单的逻辑关系彼此相关，然后由内部电路（CSM）再现; 然后将两个领域（下一个微指令正确延迟的）进行比较，并且可能的差异检测单向和不正确的排序错误。 通过某些内部电路（STK1，INC1）的特定实现和其他的复制（RCT，SEL）来检测其他错误。

    A METHOD AND APPARATUS FOR DETECTING ERRORS IN DATA OUTPUT FROM MEMORY AND A DEVICE FAILURE IN THE MEMORY
    18.
    发明授权
    A METHOD AND APPARATUS FOR DETECTING ERRORS IN DATA OUTPUT FROM MEMORY AND A DEVICE FAILURE IN THE MEMORY 有权
    方法和设备内存数据错误检测和存储器模块故障检测

    公开(公告)号：EP1141830B1

    公开(公告)日：2005-03-02

    申请号：EP99966405.5

    申请日：1999-12-22

    Applicant: INTEL CORPORATION

    Inventor： HOLMAN, Thomas, J. ,  MACWILLIAMS, Peter, D.

    IPC: G06F11/10

    CPC classification number: G06F11/1028 ,  G06F11/1036

    Abstract: A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.

    Self-checking memory cell array apparatus
    20.
    发明公开
    Self-checking memory cell array apparatus 失效
    Apparat mitselbstüberprüfendemSpeicherzellen-Bereich。

    公开(公告)号：EP0405280A2

    公开(公告)日：1991-01-02

    申请号：EP90111450.4

    申请日：1990-06-18

    Applicant: MOTOROLA, INC.

    Inventor： Corrigan, Gerald

    IPC: G11C29/00 ,  G11C11/21

    CPC classification number: G11C29/74 ,  G06F11/1008 ,  G06F11/1032 ,  G06F11/1036 ,  G11C29/38

    Abstract: A totally self-checking memory cell array apparatus (30) has an array (31)of memory cells (32) selectively addressed by row and column decoders (33, 35) which receive unidirectional error detecting code signals as address inputs (34,36). Data, as a multiple bit data word (A, B, C₁, C₂), is stored in the array (31) in unidirectional error detecting code form. Cells in each row (1-8) of the array have two separate row select connection lines (45 and 45a) for coupling the cell to data and data complement (46, 46*) connections. Error detection circuits (44, 47) are provided which determine errors by comparing the data and data complement lines for each data bit read out of the array and for detecting when multiple bit data words read out of the array are not coded in a unidirectional error detecting code format. The above apparatus provides error indications in case of any unidirectional errors in the row or column input address signals or the row or column decoders, or any unidirectional error corruption of the data stored in the memory cell array. This is achieved without completely duplicating each memory cell in the array and all row and column decoder circuitry.

    Abstract translation: 完全自检存储单元阵列装置（30）具有由行和列解码器（33,35）选择性地寻址的存储单元阵列（32），它们接收作为地址输入的单向检错码信号（34,36 ）。 作为多位数据字（A，B，C1，C2）的数据以单向错误检测码形式存储在阵列（31）中。 阵列的每行（1-8）中的单元格具有两个单独的行选择连接线（45和45a），用于将单元耦合到数据和数据互补（46,46 *）连接。 提供错误检测电路（44,47），通过比较从阵列中读出的每个数据位的数据和数据补码行来确定错误，并且用于检测从阵列中读出的多个位数据字是否以单向错误编码 检测码格式。 上述装置在行或列输入地址信号或行或列解码器中的任何单向错误或存储在存储单元阵列中的数据的任何单向错误损坏的情况下提供错误指示。 这是在没有完全复制阵列中的每个存储器单元和所有行和列解码器电路的情况下实现的。

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