Abstract:
An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.
Abstract:
A power amplifier bias circuit with embedded envelope detection includes a bias circuit stage coupled to an envelope detector circuit to increases a bias provided to a power amplifier as a function of an incoming envelope signal. The envelope detector circuit includes a first source/emitter follower transistor, a current source, and a filter to generate a baseband envelope signal. The current source is coupled to an output node of the first source/emitter follower transistor and the filter is also coupled to the output node of the first source/emitter follower transistor. The bias circuit stage includes one or more replica transistors that replicate transistors of the power amplifier or power amplifier core stage, an envelope detector replica transistor and a replica of the current source of the envelope detector circuit.
Abstract:
본 발명은 무선 통신 시스템에서 전력 증폭기의 비선형적 특성을 개선하기 위한 장치 및 방법에 관한 것으로, 무선 통신 시스템에서 송신 장치는 트랜시버(transceiver)와 상기 트랜시버로부터 제공되는 신호를 증폭하는 증폭기를 포함하고, 상기 트랜시버는 상기 트랜시버로 입력되는 신호의 전력이 기준 값보다 작은 경우, 상기 전력에 대응하는 크기만큼 상기 신호의 전력을 감쇠시키는 것을 특징으로 한다. 또한, 본 발명은 상술한 실시 예와 다른 실시 예들도 포함한다.
Abstract:
An adjustable power splitter (101) includes: a power divider (105) with an input (107) and a first and second divider output (109, 111); a first adjustable phase shifter (113) and first adjustable attenuator (115) series coupled to the first divider output (109) and providing a first power output (117); and a second adjustable phase shifter (119) and second adjustable attenuator (121) series coupled to the second divider output (111) and providing a second power output (123).
Abstract:
The present invention relates to an apparatus and a method for improving nonlinearity of a power amplifier in a wireless communication system. A transmission apparatus in a wireless communication system comprises: a transceiver; and an amplifier for amplifying a signal provided from the transceiver, wherein if the power of a signal inputted into the transceiver is smaller than a reference value, the transceiver attenuates the power of the signal by an amount corresponding to the power. In addition, the present invention also includes embodiments different from the embodiment stated above.
Abstract:
An adjustable power splitter (101) includes: a power divider (105) with an input (107) and a first and second divider output (109, 111); a first adjustable phase shifter (113) and first adjustable attenuator (115) series coupled to the first divider output (109) and providing a first power output (117); and a second adjustable phase shifter (119) and second adjustable attenuator (121) series coupled to the second divider output (111) and providing a second power output (123).
Abstract:
The present invention relates to an apparatus and a method for improving nonlinearity of a power amplifier in a wireless communication system. A transmission apparatus in a wireless communication system comprises: a transceiver; and an amplifier for amplifying a signal provided from the transceiver, wherein if the power of a signal inputted into the transceiver is smaller than a reference value, the transceiver attenuates the power of the signal by an amount corresponding to the power. In addition, the present invention also includes embodiments different from the embodiment stated above.
Abstract:
An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.
Abstract:
An adjustable power splitter (101) includes: a power divider (105) with an input (107) and a first and second divider output (109, 111); a first adjustable phase shifter (113) and first adjustable attenuator (115) series coupled to the first divider output (109) and providing a first power output (117); and a second adjustable phase shifter (119) and second adjustable attenuator (121) series coupled to the second divider output (111) and providing a second power output (123).
Abstract:
Certain aspects of the present disclosure generally relate to a multi-output amplifier (400) implemented using a capacitive attenuator (414). For example, the multi-output amplifier (400) generally includes a first capacitive attenuator (414) coupled to an input node of the multi-output amplifier (400). In certain aspects, the multi-output amplifier (400) also includes a first amplification stage (416) having an input coupled to a tap node of the first capacitive attenuator (414) and an output coupled to a first output node of the multi-output amplifier (400), and a second amplification stage (418) having an output coupled to a second output node of the multi-output amplifier (400). For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage has an input coupled to a tap node of the second capacitive attenuator.