公开(公告)号：US11812553B2

公开(公告)日：2023-11-07

申请号：US17731621

申请日：2022-04-28

Applicant: Honeywell Federal Manufacturing & Technologies, LLC

Inventor： Stephen McGarry Hatch ,  Jonathan Douglas Hatch

IPC: H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K3/10 ,  H05K1/03

CPC classification number: H05K1/09 ,  H05K1/118 ,  H05K3/103 ,  H05K1/0393 ,  H05K1/11 ,  H05K1/189 ,  H05K2201/0335 ,  H05K2201/05 ,  H05K2201/1028

Abstract: A conductive trace interconnect tape for use with a printed circuit board or a flexible circuit substrate comprises a top insulating layer, an electrically conductive layer, and a bottom insulating layer. The top insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on top of the conductive trace interconnect tape. The electrically conductive layer is positioned underneath the top insulating layer. The electrically conductive layer is formed from electrically conductive material and includes electrical interconnect traces, electrical component pads, or electrically conductive planar portions. The bottom insulating layer is positioned underneath the electrically conductive layer. The bottom insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on the printed circuit board or flexible circuit substrate.

公开(公告)号：US20170135220A1

公开(公告)日：2017-05-11

申请号：US15330844

申请日：2016-11-07

Applicant: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO

Inventor： Perumal Varun Chadalavada ,  Daniel Wigdor

IPC: H05K3/02 ,  H05K1/09

CPC classification number: H05K3/027 ,  H05K1/0386 ,  H05K1/092 ,  H05K3/04 ,  H05K3/048 ,  H05K3/06 ,  H05K2201/0108 ,  H05K2201/032 ,  H05K2201/0335 ,  H05K2201/0355 ,  H05K2203/013 ,  H05K2203/0264 ,  H05K2203/0525 ,  H05K2203/0551 ,  H05K2203/068

Abstract: Film for use in preparing a printed circuit board (PCB) along with methods for making a PCB and producing a printable film are described herein. The film includes a first layer formed of a radiation-transparent material, a second layer formed of a curable adhesive material, a third layer formed of an electrically conductive material, and optionally, a fourth layer formed of an adhesive and a fifth layer formed of a removable material. Through the adhesive layers, the layers are bonded together to produce the printable film. To produce a PCB, the first layer is covered in ink distributed in a pattern representing the PCB, and the ink-covered film is exposed to radiation until the non-ink-covered portions of the second layer have cured. Then, the fifth layer is removed tearing away the electrically conductive material associated with the non-ink-covered portions of the second layer producing the PCB.

公开(公告)号：US09554462B2

公开(公告)日：2017-01-24

申请号：US14640502

申请日：2015-03-06

Applicant: IBIDEN CO., LTD.

Inventor： Katsutoshi Kitagawa

IPC: H05K1/00 ,  H05K1/02 ,  H01L23/498 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H01L23/367 ,  H01L21/48

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/367 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/032 ,  H05K1/115 ,  H05K1/18 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4655 ,  H05K2201/0335 ,  H05K2201/096

Abstract: A printed wiring board includes a multilayer core substrate, a first buildup layer formed on the multilayer core substrate and including an interlayer insulation layer and a conductive layer, a second buildup layer formed on the multilayer core substrate and including an interlayer resin insulation layer and a conductive layer, and an end-surface through hole conductor formed on side surfaces of the first and second buildup layers and core substrate such that the through hole conductor connects the conductive layers of the first and second buildup layers. The core substrate includes a first conductive layer, a middle conductive layer, a second conductive layer, a first insulation layer between the first and middle conductive layers and a second insulation layer between the second and middle conductive layers, and the middle conductive layer is connected to the through-hole conductor and has thickness greater than thicknesses of the first and second conductive layers.

Abstract translation: 印刷电路板包括：多层芯基板，形成在所述多层芯基板上并具有层间绝缘层和导电层的第一累积层，形成在所述多层芯基板上的第二累积层，其包括层间树脂绝缘层和 导电层和形成在第一和第二堆积层和芯基板的侧表面上的端表面通孔导体，使得通孔导体连接第一和第二堆积层的导电层。 芯基板包括第一导电层，中间导电层，第二导电层，第一和中间导电层之间的第一绝缘层和第二和中间导电层之间的第二绝缘层，并且中间导电层被连接 并且具有大于第一和第二导电层的厚度的厚度。

公开(公告)号：EP2903399A4

公开(公告)日：2016-07-27

申请号：EP12885910

申请日：2012-09-26

Applicant: MEIKO ELECTRONICS CO LTD

Inventor： SHIMIZU RYOICHI ,  IWAMOTO MITSUO ,  TODA MITSUAKI

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K1/188 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/82132 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/14 ,  H05K1/0269 ,  H05K1/0284 ,  H05K1/09 ,  H05K1/115 ,  H05K3/305 ,  H05K3/4007 ,  H05K2201/0335 ,  H05K2201/09154 ,  H05K2201/0939 ,  H05K2201/09472 ,  H05K2201/09918 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/063 ,  Y02P70/613 ,  Y10T29/49131

公开(公告)号：EP2713411A2

公开(公告)日：2014-04-02

申请号：EP13185895.3

申请日：2013-09-25

Applicant: LG Innotek Co., Ltd.

Inventor： TOMOHIRO, Sampei

IPC: H01L33/62 ,  H01L33/64

CPC classification number: H01L24/04 ,  H01L23/3735 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L33/382 ,  H01L33/50 ,  H01L33/62 ,  H01L33/647 ,  H01L2224/04042 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K1/0274 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/284 ,  H05K2201/0335 ,  H05K2201/09909 ,  H05K2201/10106 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A luminescence device used in a backlight unit for lighting or displaying may be provided that includes: a substrate 11 including a first electrode 12 and a second electrode 13; an LED chip disposed on the first electrode 12; and a dam 18 disposed on the substrate 11, wherein the dam 18 is disposed spaced from the LED chip 14 , wherein the substrate 11 comprises a direct copper bonding (DCB) substrate 11 including a first copper layer 2, a second copper layer 3 and a substrate body 1, and wherein the first electrode 12 and the second electrode 13 include respectively a metal film 35 which fills a void 31 of the surfaces thereof.

Abstract translation: 可以提供用于照明或显示的背光单元中的发光装置，其包括：包括第一电极12和第二电极13的基板11; 设置在第一电极12上的LED芯片; 以及设置在基板11上的坝18，其中坝18与LED芯片14间隔开设置，其中基板11包括直接铜键合（DCB）基板11，其包括第一铜层2，第二铜层3和 基板主体1，并且其中第一电极12和第二电极13分别包括填充其表面的空隙31的金属膜35。

公开(公告)号：EP2713411A3

公开(公告)日：2016-03-16

申请号：EP13185895.3

申请日：2013-09-25

Applicant: LG Innotek Co., Ltd.

Inventor： TOMOHIRO, Sampei

IPC: H01L33/62 ,  H01L33/64 ,  H01L23/373 ,  H01L33/50

CPC classification number: H01L24/04 ,  H01L23/3735 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L33/382 ,  H01L33/50 ,  H01L33/62 ,  H01L33/647 ,  H01L2224/04042 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K1/0274 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/284 ,  H05K2201/0335 ,  H05K2201/09909 ,  H05K2201/10106 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A luminescence device used in a backlight unit for lighting or displaying may be provided that includes: a substrate 11 including a first electrode 12 and a second electrode 13; an LED chip disposed on the first electrode 12; and a dam 18 disposed on the substrate 11, wherein the dam 18 is disposed spaced from the LED chip 14 , wherein the substrate 11 comprises a direct copper bonding (DCB) substrate 11 including a first copper layer 2, a second copper layer 3 and a substrate body 1, and wherein the first electrode 12 and the second electrode 13 include respectively a metal film 35 which fills a void 31 of the surfaces thereof.

公开(公告)号：EP2903399A1

公开(公告)日：2015-08-05

申请号：EP12885910.5

申请日：2012-09-26

Applicant: Meiko Electronics Co., Ltd.

Inventor： SHIMIZU, Ryoichi ,  IWAMOTO, Mitsuo ,  TODA, Mitsuaki

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K1/188 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/82132 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/14 ,  H05K1/0269 ,  H05K1/0284 ,  H05K1/09 ,  H05K1/115 ,  H05K3/305 ,  H05K3/4007 ,  H05K2201/0335 ,  H05K2201/09154 ,  H05K2201/0939 ,  H05K2201/09472 ,  H05K2201/09918 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/063 ,  Y02P70/613 ,  Y10T29/49131

Abstract: In the present invention, in a mark forming step in a manufacturing method for a component incorporated substrate in which an electronic component (14) is positioned with reference to a mark (12) formed in a copper layer (4), when an imaginary line extending from a search center (74), which is a center of a search range (72) of a sensor, to an edge side (78) of the search range (72) is represented as a search reference line (80) and an imaginary line extending, in a state in which a mark center (76), which is the center of the mark (12), is matched with the search center (74), from the mark center (76) in the same direction as the search reference line (80) and to an outer ridgeline (25) of the mark (12) is represented as a mark reference line (82), the mark (12) is formed in a shape in which the outer ridgeline (25) of the mark (12) is present in a position where a length of the mark reference line (82) is in a range of 30% or more of the search reference line (80).

Abstract translation: 在本发明中，在制造方法的标记形成工序的元件基板并入在其中的铜层（4）当虚线形成电子部件（14）被定位成与参考标记（12） 从搜索中心（74），所有这些是一个传感器的搜索范围（72）的中心，在搜索范围的边缘侧（78）延伸（72）被表示为搜索基准线（80）和在 假想延长线，在其中的状态下的标记中心（76），所有这些是标记的中心（12）与搜索中心（74）匹配时，来自在相同的方向上的中心标记（76） 搜索基准线（80）和在所述标记（12）的外脊线（25）被表示为标记参考线（82），标记（12）的形状被形成，其中所述外棱线（25）的 标记（12）是存在于一个位置，其中标记参考线（82）的长度的范围内的搜索基准线（80）的30％或更多。

公开(公告)号：US20230422405A1

公开(公告)日：2023-12-28

申请号：US18318267

申请日：2023-05-16

Applicant: SUPERC-TOUCH CORPORATION

Inventor： Hsiang-Yu LEE ,  Shang CHIN ,  Ping-Tsun LIN

IPC: H05K3/32 ,  H05K1/02

CPC classification number: H05K3/323 ,  H05K1/0278 ,  H05K1/028 ,  H05K2201/023 ,  H05K2201/0335 ,  H05K2201/095 ,  H05K2203/068

Abstract: A circuit structure for hot-press bonding includes a first substrate, a second substrate and a conductive adhesive layer. The circuit structure further includes a first conductive layer having a plurality of connection electrodes arranged on the first substrate, a second conductive layer including a plurality of backup electrodes respectively corresponding to the connection electrodes, an insulating layer arranged between the first conductive layer and the second conductive layer, and a plurality of conductive via arranged in the insulating layer and connected to corresponding connection electrodes and backup electrodes to provide current conduction paths therebetween, thus provide additional conduction path for the connection electrodes even the connection electrodes have fracture and enhance yield and connection reliability.

公开(公告)号：US20150257261A1

公开(公告)日：2015-09-10

申请号：US14640502

申请日：2015-03-06

Applicant: IBIDEN CO., LTD.

Inventor： Katsutoshi KITAGAWA

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K1/11 ,  H01L23/498 ,  H01L23/367

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/367 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/032 ,  H05K1/115 ,  H05K1/18 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4655 ,  H05K2201/0335 ,  H05K2201/096

Abstract: A printed wiring board includes a multilayer core substrate, a first buildup layer formed on the multilayer core substrate and including an interlayer insulation layer and a conductive layer, a second buildup layer formed on the multilayer core substrate and including an interlayer resin insulation layer and a conductive layer, and an end-surface through hole conductor formed on side surfaces of the first and second buildup layers and core substrate such that the through hole conductor connects the conductive layers of the first and second buildup layers. The core substrate includes a first conductive layer, a middle conductive layer, a second conductive layer, a first insulation layer between the first and middle conductive layers and a second insulation layer between the second and middle conductive layers, and the middle conductive layer is connected to the through-hole conductor and has thickness greater than thicknesses of the first and second conductive layers.

Abstract translation: 印刷电路板包括：多层芯基板，形成在所述多层芯基板上并具有层间绝缘层和导电层的第一累积层，形成在所述多层芯基板上的第二累积层，其包括层间树脂绝缘层和 导电层和形成在第一和第二堆积层和芯基板的侧表面上的端表面通孔导体，使得通孔导体连接第一和第二堆积层的导电层。 芯基板包括第一导电层，中间导电层，第二导电层，第一和中间导电层之间的第一绝缘层和第二和中间导电层之间的第二绝缘层，并且中间导电层被连接 并且具有大于第一和第二导电层的厚度的厚度。

公开(公告)号：US20150237734A1

公开(公告)日：2015-08-20

申请号：US14429741

申请日：2012-09-26

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Ryoichi Shimizu ,  Mitsuo Iwamoto ,  Mitsuaki Toda

IPC: H05K1/18 ,  H05K1/09 ,  H05K1/02 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/188 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/82132 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/14 ,  H05K1/0269 ,  H05K1/0284 ,  H05K1/09 ,  H05K1/115 ,  H05K3/305 ,  H05K3/4007 ,  H05K2201/0335 ,  H05K2201/09154 ,  H05K2201/0939 ,  H05K2201/09472 ,  H05K2201/09918 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/063 ,  Y02P70/613 ,  Y10T29/49131

Abstract: In a mark forming step in a manufacturing method for a component incorporated substrate in which an electronic component is positioned with reference to a mark formed in a copper layer, when an imaginary line extending from a search center of a search range of a sensor, to an edge side of the search range is represented as a search reference line and an imaginary line extending, in a state in which a mark center, is matched with the search center, from the mark center in the same direction as the search reference line to an outer ridgeline of the mark is represented as a mark reference line, the mark formed in a shape in which the outer ridgeline of the mark is present in a position where a length of the mark reference line is in a range of 30% or more of the search reference line.

Abstract translation: 在其中电子部件相对于形成在铜层中的标记定位的部件结合基板的制造方法中的标记形成步骤中，当从传感器的搜索范围的搜索中心延伸到假想线时， 搜索范围的边缘侧被表示为搜索参考线，并且在标记中心与搜索中心匹配的状态下从与标记中心沿与搜索基准线相同的方向延伸的假想线延伸到 标记的外脊线被表示为标记参考线，标记形成为标记的外脊线存在于标记基准线的长度在30％以上的范围内的位置的形状 的搜索参考线。