公开(公告)号：US11756956B2

公开(公告)日：2023-09-12

申请号：US16958594

申请日：2018-05-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823487 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7827 ,  H01L29/7848

Abstract: Disclosed is a semiconductor device comprising: a substrate; a vertical active region formed on the substrate and comprising a first source/drain region, a channel region, and a second source/drain region sequentially disposed in a vertical direction, the first source/drain region including a laterally extending portion extending beyond a portion of the active region above the laterally extending portion; a gate stack formed around the periphery of the channel region, the gate stack including a laterally extending portion; and a stack contact portion from above the laterally extending portion of the first source/drain region to the laterally extending portion of the first source/drain region. The stack contact portion comprises a three-layer structure sequentially disposed in the vertical direction: a lower layer portion, a middle layer portion, and an upper layer portion. The lower layer portion contains at least the same element as the first source/drain region, the middle layer portion contains at least the same element as the channel region, and the upper layer portion contains at least the same element as the second source/drain region.

公开(公告)号：US20230276637A1

公开(公告)日：2023-08-31

申请号：US18003038

申请日：2020-06-24

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Guozhong Xing ,  Huai Lin ,  Ming Liu

IPC: H10B61/00 ,  H10N52/85

CPC classification number: H10B61/10 ,  H10N52/85

Abstract: Provided are a spin orbit torque magnetic random access memory cell, a memory array and a memory, wherein the spin orbit torque magnetic random access memory cell includes: a magnetic tunnel and a selector; the selector is a two-dimensional material based selector; the magnetic tunnel junction is arranged above or below the selector; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer; the free layer is adjacent to the antiferromagnetic layer; when the selector is turned on, the memory cell is conducted, a current generates a spin current which is injected into the free layer, and a magnetization direction of the free layer is switched by the exchange bias effect between the free layer and the antiferromagnetic layer. A deterministic magnetization switching of SOT-MRAM memory cell under zero magnetic field at room temperature may be implemented without an external magnetic field by using the exchange bias effect and applying an optimized bias voltage of the magnetic tunnel junction, so as to achieve a purpose of data writing and implement SOT-MRAM memory cell with double terminal structure.

公开(公告)号：US20230269940A1

公开(公告)日：2023-08-24

申请号：US18041085

申请日：2022-07-05

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H10B43/27 ,  H10B43/10 ,  H01L23/528 ,  H10B51/10 ,  H10B51/20 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H10B43/10 ,  H10B51/10 ,  H10B51/20

Abstract: Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. The NOR-type memory device may include: a first gate stack extending vertically on a substrate, and a gate conductor layer and a memory functional layer; a first semiconductor layer surrounding a periphery of the first gate stack, extending along a sidewall of the first gate stack, and a first source/drain region, a first channel region and a second source/drain region arranged vertically in sequence; a conductive shielding layer surrounding a periphery of the first channel region; and a dielectric layer between the first channel region and the conductive shielding layer. The memory functional layer is located between the first semiconductor layer and the gate conductor layer. A memory cell is defined at an intersection of the first gate stack and the first semiconductor layer.

公开(公告)号：US20230261050A1

公开(公告)日：2023-08-17

申请号：US18059960

申请日：2022-11-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Xiaohong Cheng ,  Fei Zhao ,  Jun Luo ,  Wenwu Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/6681 ,  H01L29/7831 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate and a channel portion. The channel portion includes a first portion including a fin-shaped structure protruding with respect to the substrate and a second portion located above the first portion and spaced apart from the first portion. The second portion includes one or more nanowires or nanosheets spaced apart from each other. Source/drain portions are arranged on two opposite sides of the channel portion in a first direction and in contact with the channel portion. A gate stack extends on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion.

公开(公告)号：US11677001B2

公开(公告)日：2023-06-13

申请号：US17153842

申请日：2021-01-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L21/02293 ,  H01L21/30608 ,  H01L29/1037 ,  H01L29/66477

Abstract: The present disclosure discloses a semiconductor device with C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the same. According to the embodiments, the semiconductor device may comprise a channel portion on a substrate, the channel portion including two or more curved nanosheets or nanowires spaced apart from each other in a lateral direction relative to the substrate and each having a C-shaped cross section; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a gate stack surrounding an outer circumference of each nanosheet or nanowire in the channel portion.

公开(公告)号：US20230124011A1

公开(公告)日：2023-04-20

申请号：US18061953

申请日：2022-12-05

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong XING ,  Huai LIN ,  Di WANG ,  Long LIU ,  Kaiping ZHANG ,  Guanya WANG ,  Yan WANG ,  Xiaoxin XU ,  Ming LIU

IPC: H04L9/32 ,  H10N50/10 ,  G11C11/16 ,  H10N50/85 ,  H01F10/32 ,  G11C11/14 ,  G06F7/58 ,  H10N50/80

Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.

公开(公告)号：US11611353B2

公开(公告)日：2023-03-21

申请号：US17422050

申请日：2021-06-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Kunyu Wang ,  Li Zhou ,  Jie Chen ,  Minghui Chen ,  Ming Chen ,  Wenjing Xu ,  Chengbin Zhang

IPC: H03M3/00

Abstract: A quantizer for a sigma-delta modulator, a sigma-delta modulator, and a method of shaping noise are provided. The quantizer includes: an integrator configured to generate, in a Kth sampling period, a quantization error signal for a Kth period according to an internal signal, a quantization error signal for a (K−1)th period, a filtered quantization error signal for the (K−1)th period and a filtered quantization error signal for a (K−2)th period; an integrating capacitor configured to store the quantization error signal for the Kth period, to weight the internal signal in a (K+1)th sampling period; a passive low-pass filter configured to acquire the quantization error signal for the Kth period in a Kth discharge period, and feed back the filtered quantization error signal to the integrator in a (K+1)th sampling period and a (K+2)th sampling period; and a comparator configured to quantize the quantization error signal for the Kth period.

公开(公告)号：US20230046423A1

公开(公告)日：2023-02-16

申请号：US17821783

申请日：2022-08-23

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong XING ,  Long LIU ,  Di WANG ,  Huai LIN ,  Ming LIU

IPC: G11C11/16 ,  G11C11/54

Abstract: A magnetoresistive memory cell includes a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer. The first magnetic tunnel junction and the second magnetic tunnel junction each are disposed on the metal layer; the metal layer is configured to pass write current, a projection line of an easy axis of the first magnetic tunnel junction on a plane where the metal layer is located forms a first angle against a direction of the write current, and a projection line of an easy axis of the second magnetic tunnel junction on the plane where the metal layer is located forms a second angle against a direction opposite to the direction of the write current; the first angle and the second angle are all less than 90°; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass read current.

公开(公告)号：US11569388B2

公开(公告)日：2023-01-31

申请号：US17005088

申请日：2020-08-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Zhengyong Zhu

IPC: H01L29/78 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L27/088 ,  H01L29/10

Abstract: A multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same are disclosed. In one aspect, the FinFET includes a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.

公开(公告)号：US20230015379A1

公开(公告)日：2023-01-19

申请号：US17784544

申请日：2020-07-09

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Qing Luo ,  Pengfei JIANG ,  Hangbing LV ,  Yuan Wang ,  Ming Liu

IPC: H01G9/042 ,  H01G9/048 ,  H01G9/07

Abstract: A HfO2-based ferroelectric capacitor and a preparation method therefor, and a HfO2-based ferroelectric memory, relating to the technical field of microelectronics. The purpose of enlarging the memory window of the ferroelectric memory is achieved by inserting an Al2O3 intercalation layer having a coefficient of thermal expansion smaller than TiN between a dielectric layer and an upper electrode (TiN) of the ferroelectric capacitor. The HfO2-based ferroelectric capacitor comprises a substrate layer, a lower electrode, a dielectric layer, an Al2O3 intercalation layer, an upper electrode and a metal protection layer from bottom to top. The memory window can be increased, information misreading is effectively prevented, and therefore, the reliability of the memory is improved.