公开(公告)号：CA2940905C

公开(公告)日：2022-08-16

申请号：CA2940905

申请日：2015-03-19

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY CHARLES ,  JACOBI CHRISTIAN

IPC: G06F9/46 ,  G06F9/50

Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

公开(公告)号：ZA202103133B

公开(公告)日：2022-07-27

申请号：ZA202103133

申请日：2021-05-10

Applicant: IBM

Inventor： GIAMEI BRUCE CONRAD ,  RECKTENWALD MARTIN ,  SCHMIDT DONALD WILLIAM ,  SLEGEL TIMOTHY ,  PURANIK ADITYA NITIN ,  FARRELL MARK ,  JACOBI CHRISTIAN ,  BRADBURY JONATHAN ,  ZOELLIN CHRISTIAN GERHARD

Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

公开(公告)号：ZA201904787B

公开(公告)日：2022-04-28

申请号：ZA201904787

申请日：2019-07-19

Applicant: IBM

Inventor： GIAMEI BRUCE CONRAD ,  JACOBI CHRISTIAN ,  SHUM CHUNG-LUNG ,  SCHMIDT DONALD WILLIAM ,  ROSA DANIEL ,  SAPORITO ANTHONY

Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.

公开(公告)号：BR112014031335B1

公开(公告)日：2022-01-04

申请号：BR112014031335

申请日：2012-11-22

Applicant: IBM

Inventor： JACOBI CHRISTIAN ,  GREINER DAN ,  MITRAN MARCEL ,  SLEGEL TIMOTHY

IPC: G06F11/07

Abstract: bloco de diagnóstico transacional. quando um abortar de uma operação ocorre num sistema de computador, e feita uma determinação para saber se a informação de diagnostico e para ser armazenado em um ou mais blocos de diagnostico de transação (tdbs). existem diferentes tipos de blocos de diagnostico de transação para aceitar informação de diagnostico, dependendo do tipo de abortar e outras considerações. como exemplos, ha uma tdb especificada pelo programa em que a informação e armazenada se um endereço valido tdb e fornecido em uma transação começar a instrução; tdb uma interrupção de programa, que e armazenado em, quando o programa e abortado devido a uma interrupção; e uma tdb interceptação programa, que e armazenado em um aborto quando resulta em uma interceptação.

公开(公告)号：DK3571578T3

公开(公告)日：2021-09-27

申请号：DK17797326

申请日：2017-11-09

Applicant: IBM

Inventor： GREINER DAN ,  SAPORITO ANTHONY ,  SHUM CHUNG-LUNG ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G06F9/30

公开(公告)号：AU2020213829A1

公开(公告)日：2021-05-20

申请号：AU2020213829

申请日：2020-01-14

Applicant: IBM

Inventor： DRIEVER PETER ,  RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON

IPC: G06F9/30 ,  G06F13/20

Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to at least one external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed. The asynchronous core-nest interface (14) comprises an input/output status array (44) with multiple input/output status buffers (24).

公开(公告)号：LT3571594T

公开(公告)日：2021-04-26

申请号：LT18700178

申请日：2018-01-03

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  SAPORITO ANTHONY ,  PAPROTSKI VOLODYMYR ,  MITRAN MARCEL

IPC: G06F12/02 ,  G06F12/14

公开(公告)号：CA2874184C

公开(公告)日：2021-01-12

申请号：CA2874184

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  RELSON PETER JEREMY ,  PHILLEY RANDALL WILLIAM

IPC: G06F9/30

Abstract: An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.

公开(公告)号：AU2018208453B2

公开(公告)日：2020-10-22

申请号：AU2018208453

申请日：2018-01-09

Applicant: IBM

Inventor： GIAMEI BRUCE CONRAD ,  JACOBI CHRISTIAN ,  SHUM CHUNG-LUNG ,  SCHMIDT DONALD WILLIAM ,  ROSA DANIEL ,  SAPORITO ANTHONY

IPC: G06F9/30

Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

公开(公告)号：AU2018209038B2

公开(公告)日：2020-10-08

申请号：AU2018209038

申请日：2018-01-03

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  SAPORITO ANTHONY ,  PAPROTSKI VOLODYMYR ,  MITRAN MARCEL

IPC: G06F9/30

Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.