公开(公告)号：EP1796445A2

公开(公告)日：2007-06-13

申请号：EP07002566.3

申请日：1997-06-12

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo ,  Kawamura, Yoichiro

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/34 ,  H01L23/498 ,  H01L23/538

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2203/0156 ,  H05K2203/0338 ,  H05K2203/0405 ,  H05K2203/043 ,  H01L2924/00

Abstract: A multilayer printed circuit board comprising a core substrate, multilayer wiring layers formed on the substrate by alternately laminating an interlaminar insulating layer and conductor pattern and a group of solder pads having solder bumps planarly arranged on an outermost surface of the multilayer wiring layers, characterized in that first, the solder pads located from first row to fifth row from an outer position of the solder pad group are constructed with flat pads connected to conductor patterns located on the outermost surface and having solder bumps formed on surfaces of the pads, while the solder pad group other than these solder pads are constructed with viaholes connected to a flat innerlayer pad group located in an inner layer and having solder bumps formed in recess portions of the viaholes and, second, the solder pads located from first row to fifth row from an outer position of the innerlayer pad group are constructed with flat pads connected to conductor patterns in the same layer as the innerlayer pad group, while the innerlayer pad group other than these pads are constituted with flat pads connected to a further innerlayer flat pad group located inward the above innerlayer through viaholes and, third, the layer having the structure of the above second feature is at least one layer.

Abstract translation: 一种多层印刷电路板，包括芯基板，通过交替层叠层间绝缘层和导体图案而形成在所述基板上的多层布线层和具有平面布置在所述多层布线层的最外表面上的焊料凸块的一组焊料焊盘，其特征在于， 首先，从焊料焊盘组的外部位置开始位于第一行至第五行的焊盘构造为连接到位于最外表面上并且在焊盘表面上形成焊料凸块的导体图案的平坦焊盘，而焊料 除了这些焊盘之外的焊盘组构造有连接到位于内层中的平坦内层焊盘组的通孔，并且具有形成在通孔的凹部中的焊料凸块，以及第二焊盘从第一行至第五行位于 内层焊盘组的外部位置由连接到导体图案中的平坦焊盘构成 与内层垫组相同，而除了这些垫之外的内层垫组由通过通孔连接到位于上述内层的另一内层平垫组的平垫构成，第三，具有上述第二结构的层 功能至少有一层。

公开(公告)号：EP1763294A1

公开(公告)日：2007-03-14

申请号：EP06300939.3

申请日：2006-09-12

Applicant: Alcatel

Inventor： Brown, Paul James

IPC: H05K1/11 ,  H01L23/498

CPC classification number: H05K1/112 ,  G06F17/5068 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method for optimizing area array device pin utilization and reducing the number of layers on a multilayered PCB comprising: preparing a package of BGA pin-out maps which anticipate the effect of existing fixed pins and derives the resulting optimum pin location assignment. Each pin-out map includes an indication of the best routing for circuits from a given component to be mounted to a PCB. Applying the package of pin-out maps during an area array pin assignment phase, thereby making an area array package capable of supporting the optimum routing configuration proposed by the pin-out maps. Applying the package of pin-out maps during a PCB design phase so that the optimum circuit routing to each pin is achieved, thereby completing the strategy layed out by the proposed pin-out maps, resulting in a lower number of PCB layers.

Abstract translation: 一种用于优化区域阵列器件引脚利用率并减少多层PCB上的层数的方法，包括：准备一组BGA引脚输出图，其预测现有固定引脚的影响并导出所得到的最佳引脚位置分配。 每个引脚映射图包括从要安装到PCB的给定组件的电路的最佳路由的指示。 在区域阵列引脚分配阶段期间应用pin-out映射的封装，从而使得能够支持由pin-out映射提出的最佳路由配置的区域阵列封装。 在PCB设计阶段应用引脚输出映射的封装，以便实现对每个引脚的最佳电路布线，从而完成所提出的引脚映射图所制定的策略，导致PCB层数较少。

公开(公告)号：EP1397031A3

公开(公告)日：2005-01-19

申请号：EP03023330.8

申请日：1996-09-12

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo ,  Kawamura, Yoichiro ,  Mori, Yoji

IPC: H01L23/12 ,  H05K1/03 ,  H05K1/11

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R12/523 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/114 ,  H05K3/184 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0212 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09727 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: A board for mounting electronic circuit parts includes a first connection terminal group including a plurality of connection terminals densely formed on the top surface of a substrate having through holes formed therein, and a second connection terminal group including a plurality of connection terminals formed at at least the peripheral portion of a back surface of the substrate. The first connection terminal group is connected to the second connection terminal group by way of the through holes. A build-up multilayer interconnection layer having via holes is formed on the top surface of the substrate, so that the first connection terminal group is connected to the second connection terminal group through the build-up multilayer interconnection layer and the through holes. According to another aspect, each signal line on the top surface of the build-up multilayer interconnection layer comprises a plurality of wiring patterns having different widths and a taper-shaped pattern that connects those wiring patterns together and whose width continuously changes. Each signal line has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density.

公开(公告)号：EP1467604A2

公开(公告)日：2004-10-13

申请号：EP04252038.7

申请日：2004-04-06

Applicant: Nortel Networks Limited

Inventor： Duxbury, Guy ,  Wyrzkowska, Aneta ,  Difilippo, Luigi ,  Kwong, Herman

IPC: H05K1/11 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49016 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Techniques for reducing the number of layers in a multilayer signal routing device (10) are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method wherein the multilayer signal routing device (10) has a plurality of electrically conductive signal path layers (16) for routing a plurality of electrical signals thereon. The method may comprise forming a plurality of electrically conductive vias (26) in the multilayer signal routing device for electrically connecting at least two of the plurality of electrically conductive signal path layers (16), wherein the plurality of vias (26) are arranged so as to form at least one channel in at least one other of the plurality of electrically conductive signal path layers (16). The method may also comprise grouping at least a portion of the plurality of electrical signals based at least in part upon their proximity to the at least one channel so that they may be efficiently routed therein.

Abstract translation: 用于减少在多层信号路由装置（10）的层的数量的技术是游离缺失盘。 在一个特定的示例性实施方式，所述技术可被实现为worin多层信号路由装置（10）具有导电信号路径的层（16），用于在其上的路由的电信号的多个的多个方法。 该方法可以包括形成在用于电多层信号路由装置导电过孔（26）的连接的至少两个导电信号路径的层（16）的多个复数，worin通孔的多元性（26）被布置成 以在至少一个其它导电信号路径的层（16）的所述多个形成至少一个通道。 因此，该方法可以包括在它们靠近所述至少一个信道分组的至少一个在至少部分地基于电信号的多个部分，从而thatthey可以有效地。其中路由。

公开(公告)号：EP1434473A2

公开(公告)日：2004-06-30

申请号：EP03394085.9

申请日：2003-09-12

Applicant: Nortel Networks Limited

Inventor： Duxbury, Guy A. ,  Kwong, Herman ,  Wyrzykowska, Aneta ,  Difilippo, Luigi G.

IPC: H05K1/11 ,  H05K3/46 ,  H01L23/498

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A technique for reducing the number of layers in a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for reducing the number of layers in a multilayer signal routing device having a plurality of electrically conductive signal path layers for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer signal routing device. In such a case, the method comprises routing electrical signals on the plurality of electrically conductive signal path layers in the multilayer signal routing device for connection to and from a high density electrically conductive contact array package based at least in part upon at least one of an electrically conductive contact signal type characteristic and an electrically conductive contact signal direction characteristic.

Abstract translation: 公开了一种用于减少多层信号路由设备中的层数的技术。 在一个特定示例性实施例中，该技术可以被实现为用于减少具有多个导电信号路径层（16）的多层信号路由设备（10）中的层数的方法，用于将电信号路由至少 安装在所述多层信号路由装置（10）的表面上的一个电子部件。 在这种情况下，该方法包括在多层信号路由设备（10）中的多个导电信号路径层（16）上布置电信号，用于至少部分地连接到高密度导电触点阵列封装 基于导电接触信号型特性和导电接触信号方向特性中的至少一种。

公开(公告)号：EP1210849A1

公开(公告)日：2002-06-05

申请号：EP00953287.0

申请日：2000-08-10

Applicant: Ford Motor Company

Inventor： ACHARI, Achyuta ,  BAKER, Jay, DeAvis ,  LI, Delin ,  NATION, Brenda, Joyce ,  TRUBLOWSKI, John

IPC: H05K1/11 ,  H05K3/36

CPC classification number: H05K3/361 ,  H05K1/0292 ,  H05K1/0295 ,  H05K1/117 ,  H05K2201/09227 ,  H05K2201/09954

Abstract: A multi-connectable printed circuit assembly, comprising: (a) a printed circuit substrate (11) having a first edge (22) and first and second edge regions (44/55), wherein at least the first edge region (44) is defined along the first edge (22); (b) a first array (77) of electrical connection features (66) disposed on or within the substrate proximate the first edge region (44); (c) a second array (88) of electrical connection features (66) disposed on or within the substrate proximate the second edge region (55), wherein the second array (88) is substantially a duplication or a mirror image of the first array (77); and (d) a plurality of circuit traces (99) disposed on or within the substrate such that each electrical connection feature (66) of the first array (77) is connected by one of the circuit traces (99) to a corresponding electrical connection feature (66) of the second array (88).

公开(公告)号：EP1083779A1

公开(公告)日：2001-03-14

申请号：EP99919584.5

申请日：1999-05-13

Applicant: IBIDEN CO., LTD.

Inventor： HIROSE, Naohiro, Ogaki-kita-kojou, Ibiden K. K. ,  KARIYA, Takashi, Ogaki-kita-kojou, Ibiden K. K. ,  MORI, Yoji, Ogaki-kita-kojou, Ibiden K. K.

IPC: H05K3/46 ,  H05K1/02 ,  H05K3/18

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90° in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract translation: 在布线图案58b，58c和58d的交叉部分X中，在构成拐角部分C等于或小于90度的部分上加入一个纸条F，并形成布线图案58。 由于添加了文件F，所以布线图案不会变薄，并且在交叉部分X中不会断开。另外，由于没有集中到交叉部分X的应力，布线图案中不会导致断开，也没有气泡 留在布线图案的交叉部分X和层间树脂绝缘层之间，从而提高了印刷线路板的可靠性。

公开(公告)号：EP0883173A1

公开(公告)日：1998-12-09

申请号：EP96930376.7

申请日：1996-09-12

Applicant: Ibiden Co., Ltd.

Inventor： ASAI, Motoo ,  KAWAMURA, Yoichiro ,  MORI, Yoji

IPC: H01L23/12 ,  H05K1/03

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R12/523 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/114 ,  H05K3/184 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0212 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09727 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: A board for mounting electronic circuit parts includes a first connection terminal group including a plurality of connection terminals densely formed on the top surface of a substrate having through holes formed therein, and a second connection terminal group including a plurality of connection terminals formed at at least the peripheral portion of a back surface of the substrate. The first connection terminal group is connected to the second connection terminal group by way of the through holes. A build-up multilayer interconnection layer having via holes is formed on the top surface of the substrate, so that the first connection terminal group is connected to the second connection terminal group through the build-up multilayer interconnection layer and the through holes. According to another aspect, each signal line on the top surface of the build-up multilayer interconnection layer comprises a plurality of wiring patterns having different widths and a taper-shaped pattern that connects those wiring patterns together and whose width continuously changes. Each signal line has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density.

Abstract translation: 用于安装电子电路部件的板包括：第一连接端子组，包括密实地形成在其上形成有通孔的基板的顶表面上的多个连接端子，以及包括至少形成有多个连接端子的第二连接端子组 衬底的背面的周边部分。 第一连接端子组通过通孔连接到第二连接端子组。 在基板的顶面形成有具有通孔的积层多层互连层，使得第一连接端子组通过积层多层互连层和通孔与第二连接端子组连接。 根据另一方面，积层多层互连层的顶表面上的每个信号线包括具有不同宽度的多个布线图案和将这些布线图案连接在一起并且其宽度连续变化的锥形图案。 每个信号线在具有比布线密度相对较低的区域具有相对高的布线密度的区域上具有较小的宽度。

公开(公告)号：EP0840541A1

公开(公告)日：1998-05-06

申请号：EP97203420.1

申请日：1997-11-04

Applicant: TULIP COMPUTERS INTERNATIONAL B.V.

Inventor： Grotenhuis, Robert-Jan

IPC: H05K7/14

CPC classification number: H05K7/1422 ,  H05K1/0295 ,  H05K1/117 ,  H05K2201/09227 ,  H05K2201/09954

Abstract: Disclosed is a video card (120) which comprises a substantially rectangular, sheetlike component support(29) with a lower edge (21) and a rear edge (22). The video card (120) has a first edge connector (25) formed as a projecting portion (23) starting from the lower edge (21) of the component support (29), which projecting portion (23) is provided with terminals (24). The video card (120) further has a sub-D connector (26) provided with terminals (28), arranged at the rear edge (22) of the component support (29). According to the present invention, the video card (120) further has a second edge connector (130) formed as a projecting portion (131) starting from the lower edge (21) of the component support (29), which projecting portion (131) is provided with terminals (132), and the terminals (28) of the sub-D connector (26) are coupled to terminals (132) of the second edge connector (130).

Abstract translation: 公开了一种视频卡（120），其包括具有下边缘（21）和后边缘（22）的大致矩形的片状部件支撑件（29）。 视频卡（120）具有从部件支撑件（29）的下边缘（21）开始形成为突出部分（23）的第一边缘连接器（25），该突出部分（23）设置有端子（24） ）。 视频卡（120）还具有设置在部件支撑件（29）的后边缘（22）处的端子（28）的副D连接器（26）。 根据本发明，视频卡（120）还具有从部件支撑件（29）的下边缘（21）开始形成为突出部分（131）的第二边缘连接器（130），该突出部分 ）设置有端子（132），并且副D连接器（26）的端子（28）联接到第二边缘连接器（130）的端子（132）。

公开(公告)号：EP0765053A3

公开(公告)日：1998-04-08

申请号：EP96110493.2

申请日：1996-06-28

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA ,  ADVANCED DISPLAY INC.

Inventor： Yamagishi, Keitarou ,  Gotoh, Akio ,  Miura, Akihiro ,  Mukai, Eiji ,  Gofuku, Eishi, c/o Advanced Display Inc.

IPC: H04K1/00 ,  G02F1/13

CPC classification number: H05K1/112 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/361 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10136

Abstract: The signal connecting through vias are provided on an edge side of a multilayer printed circuit board along a longitudinal direction thereof, and the signal wiring of the respective layers of the signal wiring layer is inclined with respected to the arrangement of the through vias.

Abstract translation: 沿纵向方向设置通孔连接所述信号上在多层印刷电路板的边缘侧，和信号布线层的respectivement层的信号布线是倾斜的遵守，以通孔的布置。