公开(公告)号：US20110062563A1

公开(公告)日：2011-03-17

申请号：US12560727

申请日：2009-09-16

Applicant: Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

Inventor： Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

IPC: H01L23/495 ,  H01L21/44 ,  H01L23/52

CPC classification number: H05K3/28 ,  G11C16/0483 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/83191 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/24 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K3/3452 ,  H05K2201/0166 ,  H05K2201/0769 ,  H05K2201/10159 ,  H05K2201/10575 ,  H05K2203/049 ,  H05K2203/1316 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Mobile ion diffusion causes a shift in the threshold voltage of non-volatile storage elements in a memory chip, such as during an assembly process of the memory chip. To reduce or avoid such shifts, a coating can be applied to a printed circuit board substrate or a leader frame to which the memory chip is surface mounted. An acrylic resin coating having a thickness of about 10 μm may be used. A memory chip is attached to the coating using an adhesive film. Stacked chips may be used as well. Another approach provides metal barrier traces over copper traces of the printed circuit board, within a solder mask layer. The metal barrier traces are fabricated in the same pattern as the copper traces but are wider so that they at least partially envelop and surround the copper traces. Corresponding apparatuses and fabrication processes are provided.

Abstract translation: 移动离子扩散导致存储芯片中的非易失性存储元件的阈值电压的偏移，例如在存储器芯片的组装过程中。 为了减少或避免这种偏移，可以将涂层施加到印刷电路板基板或表面安装存储芯片的引导框架。 可以使用厚度约为10μm的丙烯酸树脂涂层。 使用粘合膜将记忆芯片附着到涂层上。 也可以使用堆叠的芯片。 另一种方法在焊接掩模层内提供印刷电路板的铜迹线上的金属阻挡迹线。 金属阻挡迹线以与铜迹线相同的图案制造，但是更宽，使得它们至少部分地包围和包围铜迹线。 提供相应的装置和制造工艺。

公开(公告)号：US20100208440A1

公开(公告)日：2010-08-19

申请号：US12771501

申请日：2010-04-30

Applicant: Joel S. Peiffer ,  Nelson B. O'Bryan

Inventor： Joel S. Peiffer ,  Nelson B. O'Bryan

IPC: H05K1/18 ,  H01C1/012 ,  H01C17/00

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/16 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/0166 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A passive electrical article includes a first electrically conductive substrate having a major surface and a second electrically conductive substrate having a major surface. The major surface of the second substrate faces the major surface of the first substrate. An electrically resistive layer is on at least one of the major surface of the first substrate and the major surface of the second substrate. An electrically insulative layer is between the first and second substrates and in contact with the electrically resistive layer. The insulative layer is a polymer having a thickness ranging from about 1 μm to about 20 μm. The insulative layer has a substantially constant thickness.

Abstract translation: 无源电器件包括具有主表面的第一导电衬底和具有主表面的第二导电衬底。 第二基板的主表面面向第一基板的主表面。 电阻层位于第一基板的主表面和第二基板的主表面中的至少一个上。 电绝缘层位于第一和第二基板之间并与电阻层接触。 绝缘层是厚度为约1μm至约20μm的聚合物。 绝缘层具有基本恒定的厚度。

公开(公告)号：US20100065960A1

公开(公告)日：2010-03-18

申请号：US12557882

申请日：2009-09-11

Applicant: Katsuyoshi MINO ,  Masaru Kanakubo ,  Masami Motegi

Inventor： Katsuyoshi MINO ,  Masaru Kanakubo ,  Masami Motegi

IPC: H01L23/48 ,  H01L21/78 ,  H01L21/56 ,  H01L21/50

CPC classification number: H01L23/49531 ,  H01L21/565 ,  H01L23/49551 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/0554 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/056 ,  H05K3/284 ,  H05K2201/0166 ,  H05K2203/1316 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Provided is a circuit device manufacturing method for coating a bottom surface of a circuit board with a thin coating of sealing resin. In the present invention, a circuit board having a circuit element such as a semiconductor element embedded therein is placed in a molding die, and a resin sheet containing a thermosetting resin is interposed between the circuit board and a bottom surface of an inner wall of the molding die. Under this condition, the molding die is heated to about 180° C., and a sealing resin in liquid form is injected through a gate. Thereby, the bottom surface of the circuit board can be coated with a thin coating of the sealing resin made of the molten resin sheet.

Abstract translation: 提供了一种用薄型密封树脂涂覆电路板底面的电路器件制造方法。 在本发明中，将具有嵌入其中的半导体元件等电路元件的电路基板放置在成型模具中，将含有热固化性树脂的树脂片插入在电路基板与内部的内壁的底面之间 成型模具。 在这种条件下，将模具加热至约180℃，并通过浇口注入液体形式的密封树脂。 由此，电路板的底面可以涂覆有由熔融树脂片制成的密封树脂的薄涂层。

公开(公告)号：US07603769B2

公开(公告)日：2009-10-20

申请号：US11901162

申请日：2007-09-14

Applicant: My Jang

Inventor： My Jang

IPC: H05K3/30

CPC classification number: H05K3/3442 ,  H05K3/303 ,  H05K2201/0166 ,  H05K2201/09472 ,  H05K2201/10393 ,  H05K2201/10636 ,  H05K2201/2018 ,  H05K2203/0169 ,  H05K2203/0594 ,  H05K2203/0769 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49171

Abstract: Methods of coupling a surface mount device with a substrate such as a printed circuit, for example, are disclosed. A method, according to one aspect, may include coupling a holder with a substrate such that terminals of the substrate are included in an opening of the holder, mounting an electronic device over the terminals with a conductive bonding material disposed there between, heating the conductive bonding material to its melting point, and cooling the conductive bonding material.

Abstract translation: 公开了将表面安装器件与印刷电路等基板连接的方法。 根据一个方面的一种方法可以包括将保持器与衬底连接，使得衬底的端子包括在保持器的开口中，将电子器件安装在端子之间，其中设置有导电接合材料，加热导电 将材料接合到其熔点，并冷却导电接合材料。

公开(公告)号：US20080314628A1

公开(公告)日：2008-12-25

申请号：US12021698

申请日：2008-01-29

Applicant: Ki Yong SONG ,  Sung-Hen CHO ,  Jun Hyuk MOON ,  Chang Oh JEONG ,  Hong Long NING

Inventor： Ki Yong SONG ,  Sung-Hen CHO ,  Jun Hyuk MOON ,  Chang Oh JEONG ,  Hong Long NING

IPC: H05K1/09 ,  B05D5/12

CPC classification number: H01L27/1288 ,  G02F1/136286 ,  G02F2001/136295 ,  G02F2202/42 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/048 ,  H05K3/107 ,  H05K3/184 ,  H05K3/388 ,  H05K2201/0166 ,  H05K2203/0565

Abstract: Disclosed is a method of forming a metal pattern, the method comprising depositing a dielectric substrate on a supporting substrate; forming a latent mask pattern of a metal pattern on the dielectric substrate; etching the dielectric substrate exposed by the latent mask pattern; forming a seed layer on the supporting substrate by activating the supporting substrate; removing the latent mask pattern and the portion of the seed layer disposed on the latent mask pattern through a lift-off process; and plating a metal layer on the patterned seed layer.

Abstract translation: 公开了一种形成金属图案的方法，所述方法包括在支撑衬底上沉积电介质衬底; 在所述电介质基板上形成金属图案的潜像图案; 蚀刻由潜像图案曝光的电介质基片; 通过激活支撑衬底在支撑衬底上形成种子层; 通过剥离过程去除潜在掩模图案和设置在潜像图案上的种子层的部分; 并且在图案化种子层上镀覆金属层。

公开(公告)号：US20080005901A1

公开(公告)日：2008-01-10

申请号：US11901162

申请日：2007-09-14

Applicant: My Jang

Inventor： My Jang

IPC: H05K3/34 ,  H05K1/16 ,  H05K3/30

CPC classification number: H05K3/3442 ,  H05K3/303 ,  H05K2201/0166 ,  H05K2201/09472 ,  H05K2201/10393 ,  H05K2201/10636 ,  H05K2201/2018 ,  H05K2203/0169 ,  H05K2203/0594 ,  H05K2203/0769 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49171

Abstract: Methods and apparatus to couple a device, such as, for example, a surface mount device, with a substrate, such as, for example, a printed circuit, are disclosed. An apparatus, according to one aspect, may include a substrate, a plurality of terminals coupled with the substrate, a conductive bonding material coupled with the plurality of terminals, an electronic device coupled with the conductive bonding material, and a holder that is coupled with the substrate to hold the electronic device. A method, according to one aspect, may include coupling a holder with a substrate such that terminals of the substrate are included in an opening of the holder, mounting an electronic device over the terminals with a conductive bonding material disposed therebetween, heating the conductive bonding material to its melting point, and cooling the conductive bonding material.

Abstract translation: 公开了将诸如例如表面贴装装置的装置与衬底（例如印刷电路）耦合的方法和装置。 根据一个方面的装置可以包括衬底，与衬底耦合的多个端子，与多个端子耦合的导电接合材料，与导电接合材料耦合的电子器件，以及与 保持电子设备的基板。 根据一个方面的一种方法可以包括将保持器与衬底连接，使得衬底的端子包括在保持器的开口中，将电子器件安装在端子之间，其间设置有导电接合材料，加热导电接合 材料到其熔点，并冷却导电接合材料。

公开(公告)号：US20070163111A1

公开(公告)日：2007-07-19

申请号：US11728406

申请日：2007-03-26

Applicant: Yutaka Kaneda

Inventor： Yutaka Kaneda

IPC: H05K3/20

CPC classification number: H05K3/0002 ,  H05K1/0393 ,  H05K3/002 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4635 ,  H05K2201/0166 ,  H05K2201/0367 ,  H05K2203/056 ,  H05K2203/0733 ,  H05K2203/1545 ,  Y10S428/901 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: In one embodiment, the present invention provides a process for manufacturing a multilayer flexible wiring board, which allows individual layers of wiring boards to be precisely positioned and to be readily stacked. A mask for exposure is prepared in which a plurality of pattern holes corresponding to individual layers of wiring boards of a multilayer flexible wiring board are arranged in the direction perpendicular to the transporting direction P of substrate. This mask for exposure is used to form a plurality of wiring patterns corresponding to individual layers of wiring boards of a multilayer flexible wiring board on the same sheet-like substrate.

Abstract translation: 在一个实施例中，本发明提供一种制造多层挠性布线板的方法，其允许各层布线板精确定位并容易堆叠。 制备用于曝光的掩模，其中与垂直于基板的传送方向P的方向布置与多层柔性布线板的布线板的各层相对应的多个图案孔。 该曝光用掩模用于形成与同一片状基板上的多层柔性布线基板的各层布线基板对应的多个布线图案。

公开(公告)号：US20070111561A1

公开(公告)日：2007-05-17

申请号：US11565715

申请日：2006-12-01

Applicant: Alan Wang ,  Kevin Olson ,  Thomas DiStefano

Inventor： Alan Wang ,  Kevin Olson ,  Thomas DiStefano

IPC: H01R12/00

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09554 ,  H05K2201/10446 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Provided is a method of forming a circuit board including (a) providing a first conductive sheet; (b) selectively removing one or more portions of the first conductive sheet to form a first panel having a first circuit board that is coupled to a disposable part of the first panel by at least one tab that extends from an edge of the first circuit board to an edge of the disposable part of the first panel; (c) applying an insulating coating to the first circuit board so that at least each edge of the first circuit board is covered thereby; and (d) separating the first circuit board from the disposable part in a manner whereupon at least part of the tab remains attached to the first circuit board and includes an exposed edge of the conductive sheet of the first circuit board. Circuit boards formed by the method are also provided.

Abstract translation: 提供一种形成电路板的方法，包括：（a）提供第一导电片; （b）选择性地去除所述第一导电片的一个或多个部分以形成具有第一电路板的第一面板，所述第一电路板通过从所述第一电路板的边缘延伸的至少一个接片连接到所述第一面板的一次性部分 到所述第一面板的一次性部分的边缘; （c）向第一电路板施加绝缘涂层，使得第一电路板的至少每个边缘被覆盖; 和（d）以一种方式将第一电路板与一次性部分分离，由此至少部分突片保持附接到第一电路板并且包括第一电路板的导电片的暴露边缘。 还提供了通过该方法形成的电路板。

公开(公告)号：US20060286696A1

公开(公告)日：2006-12-21

申请号：US11157531

申请日：2005-06-21

Applicant: Joel Peiffer ,  Nelson O'Bryan

Inventor： Joel Peiffer ,  Nelson O'Bryan

IPC: H01L21/00 ,  H01L33/00

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/16 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/0166 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A passive electrical article includes a first electrically conductive substrate having a major surface and a second electrically conductive substrate having a major surface. The major surface of the second substrate faces the major surface of the first substrate. An electrically resistive layer is on at least one of the major surface of the first substrate and the major surface of the second substrate. An electrically insulative layer is between the first and second substrates and in contact with the electrically resistive layer. The insulative layer is a polymer having a thickness ranging from about 1 μm to about 20 μm. The insulative layer has a substantially constant thickness.

Abstract translation: 无源电器件包括具有主表面的第一导电衬底和具有主表面的第二导电衬底。 第二基板的主表面面向第一基板的主表面。 电阻层位于第一基板的主表面和第二基板的主表面中的至少一个上。 电绝缘层位于第一和第二基板之间并与电阻层接触。 绝缘层是厚度范围为约1μm至约20μm的聚合物。 绝缘层具有基本恒定的厚度。

公开(公告)号：US07144817B2

公开(公告)日：2006-12-05

申请号：US09905052

申请日：2001-07-12

Applicant: Hiroshi Samukawa

Inventor： Hiroshi Samukawa

IPC: H01L21/302 ,  C09K13/00

CPC classification number: C08J7/12 ,  C08J2379/08 ,  G03F7/40 ,  G03F7/405 ,  H05K3/002 ,  H05K3/28 ,  H05K3/4614 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2203/0783 ,  H05K2203/0793

Abstract: The disclosure relates to methods and solutions for precisely and rapidly etching a polyimide resin layer. Etching solutions of the present invention include 3–65% by weight of a diol containing 3 to 6 carbon atoms or a triol containing 4 to 6 carbon atoms, 10–55 % by weight of an alkali compound and water in an amount of 0.75–3.0 times the amount of the alkali compound, and can be used at 65° C. or more to rapidly etch a polyimide resin layer having an imidation degree of 50–98 % without unfavorably affecting the working atmosphere. Even if the resin layer is completely imidated after etching, the etching pattern of the resulting resin layer is not deformed with a decreased contamination by impurity ions as compared with those obtained using conventional etching solutions.