公开(公告)号：EP1861857A2

公开(公告)日：2007-12-05

申请号：EP05853280.5

申请日：2005-12-07

Applicant: M-Flex Multi-Fineline Electronix, Inc.

Inventor： WHITTAKER, Ronald W. ,  GUERRA, Joe D. ,  MARCOCI, Ciprian

IPC: H01F5/00

CPC classification number: H01F27/266 ,  H01F17/0033 ,  H01F17/062 ,  H01F19/04 ,  H01F27/2804 ,  H01F41/046 ,  H01F2017/002 ,  H05K1/165 ,  H05K1/189 ,  H05K3/389 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10416 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Electrical connection between the plural levels of circuitry and multiple windings around magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.

公开(公告)号：EP1325545A4

公开(公告)日：2004-11-24

申请号：EP01975308

申请日：2001-09-24

Applicant: FLEX MULTI FINELINE ELECTRONIX

Inventor： HARDING PHILIP A

IPC: H01F41/00 ,  H01F17/00 ,  H01F17/04 ,  H01F30/00 ,  H01F37/00 ,  H01F41/04 ,  H05K1/16 ,  H05K3/06 ,  H05K3/42 ,  H05K3/46 ,  H02M1/00 ,  H01F27/28

CPC classification number: H01F41/046 ,  H01F17/0033 ,  H05K1/165 ,  H05K3/06 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/086 ,  H05K2201/09063 ,  H05K2201/097 ,  H05K2201/10416 ,  Y10S29/016 ,  Y10T29/4902 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49165

Abstract: The present invention relates to the methods of construction for inductive components of, preferably, ferromagnetic materials such as inductors, chokes, and transformers when used as an integral part of the fabrication of PCB's or FLEX's. In one preferred embodiment, holes (56, 58) are formed through a ferromagnetic substrate (50) and plated with conductive material. The arrangement of these holes, and the subsequent design that ensues, will form the inductive components within the plane of the media in which the device is formed; using the substrate (50) for a magnetic core (90). By using this approach, the inductive components can be miniaturized to physical sizes compatible with the requirements of modern surface mount technology (SMT) for integrated circuitry (IC). This process also allows these components to be fabricated using mass production techniques, thereby avoiding the need to handle discrete devices during the manufacturing process. In another preferred embodiment, a series of thin, concentric high permeability rings (315) are etched on a substrate (330) to provide high permeability transformers and inductors having minimal eddy current effects.

公开(公告)号：EP1197130B1

公开(公告)日：2003-05-21

申请号：EP00948103.7

申请日：2000-07-13

Applicant: International Business Machines Corporation

Inventor： LAUFFER, John ,  RUSSELL, David

IPC: H05K1/16 ,  H05K3/46 ,  H01F41/04

CPC classification number: H01F41/041 ,  H01F17/0033 ,  H05K1/095 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/086 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1453 ,  H05K2203/1461 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T428/24917 ,  Y10T428/2495 ,  Y10T428/24967 ,  Y10T428/24975

Abstract: Passive electrical components such as capacitors, resistors, inductors, transformers, filters and resonators are integrated into electrical circuits utilizing a process which maximizes the utilization of the planar surfaces of the substrates for high density placement of active components such as logic or memory integrated circuits. The passive components are integrated into a conventional circuit board utilizing a photoimageable dielectric material (20). The dielectric (20) is photoimaged and etched to provide one or more recesses or openings (26) for the passive devices, and photovias interconnecting the inputs and outputs of the integrated circuit board. The electronic structure comprising at least one of the passive devices integrated into a photoimaged dielectric (20) is described as well as the method of manufacturing the same.

公开(公告)号：EP0809260B1

公开(公告)日：2003-03-19

申请号：EP97108249.0

申请日：1997-05-21

Applicant: MOLEX INCORPORATED

Inventor： Noda, Atsuhito ,  Hoshino, Tetsuo

IPC: H01B7/08

CPC classification number: H01B7/0876 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/118 ,  H05K2201/09263 ,  H05K2201/097

公开(公告)号：EP1037512A3

公开(公告)日：2002-06-19

申请号：EP00105207.5

申请日：2000-03-13

Applicant: MOLEX INCORPORATED

Inventor： Brunker, David L.

IPC: H05K1/02 ,  H01B7/08

CPC classification number: H05K1/0228 ,  H01B7/0876 ,  H05K1/0219 ,  H05K1/0245 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/097

Abstract: A flexible circuit member (101) includes first and second pseudo-twisted flexible conductors (103a,103b) on a flexible dielectric substrate (102). The first pseudo-twisted conductor (103a) is on a first side of the substrate (102) and the second pseudo-twisted conductor (103b) is on a second side of the substrate (102). Each pseudo-twisted conductor includes a periodic pattern with the first pseudo-twisted conductor (103a) being shifted longitudinally relative to the second pseudo-twisted conductor (103b) by one half of a period of the periodic pattern. A set of first and second additional conductors (114a,114b) are also provided on the dielectric substrate (102). The first additional conductor (114a) is on the first side of the substrate (102) and is spaced from and generally follows the shape of the first pseudo-twisted conductor (103a). The second additional conductor (114b) is on the second side of the substrate (102) and is spaced from and generally follows the shape of the second pseudo-twisted conductor (103b). These first and second additional conductors (114a,114b) may be coupled to reference or ground potential so as to provide a grounding system for the flexible circuit member (101).

公开(公告)号：EP0880309A3

公开(公告)日：2001-08-01

申请号：EP98108818.0

申请日：1998-05-14

Applicant: NEC CORPORATION

Inventor： Tohya, Hirokazu ,  Yoshida, Shiro

IPC: H05K1/16 ,  H05K1/02

CPC classification number: H05K1/165 ,  H05K1/0231 ,  H05K1/0233 ,  H05K3/4688 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/097

Abstract: A printed board (1) has at least two conductor layers including a power supply layer (3) and a ground layer (4), and a spiral coil inductor (8a) disposed in opposite ones of the conductor layers. The spiral coil inductor (8a) has a terminal connected to a power supply line (9) of the power supply layer (3), and another terminal connected to a device power terminal (3a) disposed on one of the conductor layers and to be connected to a power supply terminal (10a) of a circuit device (10) and a terminal of a decoupling capacitor (15a). A device ground terminal (4a) is disposed on one of the conductor layers and to be connected to a ground terminal (10b) of the circuit device (10) and another terminal of the decoupling capacitor (15), the device ground terminal (10b) being connected to a ground line (13) of the ground layer (4).

公开(公告)号：EP1026927A2

公开(公告)日：2000-08-09

申请号：EP00300407.4

申请日：2000-01-20

Applicant: Ford Motor Company

Inventor： Goenka, Lakhi Nandlal

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H05K3/3421 ,  H05K2201/09381 ,  H05K2201/097 ,  H05K2201/10689 ,  Y02P70/611

Abstract: A circuit board having special bond pad configurations which mitigate against both reflow-induced skew and bond pad delamination, especially for fine-pitch applications. The circuit board comprises: (1) an electrically insulative substrate 16; and (2) a plurality of bond pads 20 disposed side-by-side in a generally straight row on the substrate, wherein the row defines a width direction therealong and a length direction orthogonal thereto. Each bond pad 20 has an overall width W as measured along the width direction and an overall length L as measured along the length direction, such that L > W. Each pad 20 also has an overall left edge 22 and an overall right edge 24 running generally along the overall length of each respective pad, such that at least one of the edges of each pad is non-straight or is oblique with respect to the length direction. The adjacent edges of adjacent pads generally dovetail, interdigitate, or otherwise conform in shape with each other, such that at least one portion of each pad has a width W min wide enough to avoid delamination of the pad, while the remainder of each pad is narrow enough that skewing of the component leads during reflow is avoided.

Abstract translation: 具有特殊接合焊盘结构的电路板，其减轻了回流引起的偏斜和接合焊盘分层，特别是对于精细间距应用。 电路板包括：（1）电绝缘基板16; 以及（2）在基板上以大致直线列并排配置的多个接合焊盘20，其中该行限定宽度方向和与其正交的长度方向。 每个接合焊盘20具有沿着宽度方向测量的总宽度W和沿长度方向测量的总长度L，使得L> W。每个焊盘20还具有整体左边缘22和整个右边缘24运行 通常沿着每个相应焊盘的总长度，使得每个焊盘的至少一个边缘是非直的或相对于长度方向倾斜的。 相邻焊盘的​​相邻边缘通常在形状上彼此相交，相互指向或以其它方式相符合，使得每个焊盘的至少一部分宽度足够宽以避免焊盘的分层，而每个焊盘的其余部分是窄的 足以避免在回流期间元件的偏斜导致。

公开(公告)号：EP0880150A3

公开(公告)日：1999-08-18

申请号：EP98109129.1

申请日：1998-05-19

Applicant: NEC CORPORATION

Inventor： Tohya, Hirokazu ,  Yoshida, Shiro ,  Shimada, Yuzo

IPC: H01F17/00

CPC classification number: H01F17/0013 ,  H05K1/0233 ,  H05K1/165 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/097

Abstract: An insulative magnetic layer is disposed between a power source conductor layer and a ground conductor layer of a printed-wiring board. Two pieces of conductors are formed by cutting out a part of the power source conductor layer. Another two pieces of conductors are formed by cutting out a part of the ground conductor layer. The former conductors and the latter conductors are connected by five viaholes. A spiral coil inductor of a spiral form is formed in this way. This inductor has the strengthened inductance owing to the insulative magnetic layer provided therein.

公开(公告)号：EP0918355A2

公开(公告)日：1999-05-26

申请号：EP98203298.9

申请日：1998-09-29

Applicant: DELCO ELECTRONICS CORPORATION

Inventor： Cornell, Ralph Edward ,  Erickson, Curtis A. ,  Vaidyanthan, Aparna

IPC: H01L23/485

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K3/3436 ,  H05K2201/09381 ,  H05K2201/097 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A surface mount circuit device (110), such as a flip chip, of the type which is attached to a conductor pattern (126) with solder bump connections (120). The solder bump connections (120) are formed by reflowing solder on shaped input/output pads (112) on the device (110), with the shape of the pads (112) being tailored to favorably affect optimal distribution, shape and height of the solder bump connections (120) following reflow soldering of the device (110) to the conductor pattern (126). The solder bump connections (120) are preferably characterized by a shape that increases the stand-off height of the device (110). The shaped solder bump connections (120) also promote stress relief during thermal cycling, improve mechanical bonding, allow better penetration of cleaning solutions, and improve flow of encapsulation materials between the device (110) and its substrate (122).

公开(公告)号：EP0403288A3

公开(公告)日：1991-05-22

申请号：EP90306520.9

申请日：1990-06-14

Applicant: GRAPHICO CO. LTD.

Inventor： Takashima, Tokuhei

IPC: G06F13/40 ,  G06F1/16 ,  H05K7/14

CPC classification number: H05K1/0228 ,  G06F13/409 ,  H05K1/0245 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/097

Abstract: Disclosed is a radial type of parallel system bus structure using bus wire-printed disks (15) each having printed signal conductors (7) of equal length extending radially from a common contact centre . Each printed signal conductor comprises two twisted conductor lines, and each conductor line consists of many segments disposed alternately on opposite surfaces of the disk, the successive segments of each line being connected by plating in through-holes(10) in the disk. The radial arrangement of signal conductors permits connection of selected CPU boards via equal length of signal path. Also, the use of twisted conductor lines improves the signal transmission characteristics of the bus in high-frequency range.