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251.发明公开Method of manufacturing an external force detection sensor 审中-公开Verfahren zur Herstellung eines Sensors zur Detektion deräußerenKraftgröße
公开(公告)号：EP1655610A2
公开(公告)日：2006-05-10
申请号：EP06001026.1
申请日：2000-04-14
Applicant: MURATA MANUFACTURING CO., LTD.
IPC: G01P15/08
CPC classification number: G01C19/5719 , B81B2201/025 , B81C1/00579 , B81C1/00587 , B81C2201/0132 , B81C2201/014 , G01P15/0802 , G01P15/125 , G01P2015/0814 , Y10S148/012 , Y10S148/135 , Y10S148/159
Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole (20) dry etching of an element substrate (3), and an electrically conductive material is used as an etching stop layer (18) during the dry etching.
Abstract translation: 一种制造外力检测传感器的方法，其中通过元件基板（3）的通孔（20）干蚀刻形成传感器元件，并且导电材料被用作蚀刻停止层（18）期间 干蚀刻。
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公开(公告)号：EP1510864A2
公开(公告)日：2005-03-02
申请号：EP04026039.0
申请日：2000-07-13
Applicant: Input/Output, Inc.
Inventor： Yu, Lianzhong , Ried, Robert P. , Goldberg, Howard D. , Yu, Duli
IPC: G03F7/00
CPC classification number: G02B26/0816 , B81B2201/042 , B81C1/00396 , B81C2201/0132 , B81C2201/0133 , B81C2203/0109 , C23F1/02
Abstract: The present invention provides merged-mask processes for fabricating micromachined devices in general and mirrored assemblies for use in optical scanning devices in particular. A method of fabricating a three dimensional structure, comprising, providing a substrate, applying a layer of a first masking material onto the substrate, applying a layer of a second masking material onto the layer of the first masking material, patterning the layer of the second masking material, applying a layer of a third masking material onto the portions not covered by the patterned layer of the second masking material, the layer of the third masking material is at least as thick as the combined thickness of the layers of the first and second masking materials, patterning the layers of the first and third masking materials, etching the exposed portions of the substrate, etching the exposed portions of the layers of the first and third masking materials and etching the exposed portions of the substrate.
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公开(公告)号：EP1196788B1
公开(公告)日：2004-12-22
申请号：EP00945370.5
申请日：2000-07-13
Applicant: Input/Output, Inc.
Inventor： YU, Lianzhong , RIED, Robert, P. , GOLDBERG, Howard, D. , YU, Duli
CPC classification number: G02B26/0816 , B81B2201/042 , B81C1/00396 , B81C2201/0132 , B81C2201/0133 , B81C2203/0109 , C23F1/02
Abstract: The present invention provides merged-mask processes for fabricating micro-machined devices in general and mirrored assemblies for use in optical scanning devices in particular. The process includes (a) providing a substrate having a predetermined thickness; (b) applying a first masking layer on a first portion of the substrate and a second masking layer on a second portion of the substrate, said second masking layer being at least as thick as the first masking layer; (c) etching a portion of the second masking layer to provide a first exposed portion of the substrate; (d) etching the first exposed portion of the substrate to a first depth; (e) etching the second masking layer to provide a second exposed portion of the substrate; and (f) etching simultaneously the first exposed portion of the substrate to a second depth and the second exposed portion of the substrate to a first depth. The process further comprises patterning the first masking layer before applying the second masking layer to provide the second portion of the substrate for etching and etching the first masking layer to expose the second portion of the substrate. The first and second masking layers are applied prior to etching the substrate.
Abstract translation: 本发明提供了用于一般地制造微机械装置和特别是用于光学扫描装置的镜面组件的合并掩模工艺。 一种制造三维结构的方法，包括：提供衬底，将第一掩蔽材料层施加到所述衬底上，将第二掩蔽材料层施加到所述第一掩模材料的所述层上，将所述第二掩模材料的所述层 掩模材料，将第三掩模材料层施加到未被第二掩模材料的图案化层覆盖的部分上，第三掩模材料的层至少与第一和第二掩模材料的层的组合厚度一样厚 掩模材料，图案化第一和第三掩模材料的层，蚀刻衬底的暴露部分，蚀刻第一和第三掩模材料的层的暴露部分并蚀刻衬底的暴露部分。
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公开(公告)号：EP1046917A3
公开(公告)日：2004-08-11
申请号：EP00108261.9
申请日：2000-04-14
Applicant: Murata Manufacturing Co., Ltd.
IPC: G01P15/08
CPC classification number: G01C19/5719 , B81B2201/025 , B81C1/00579 , B81C1/00587 , B81C2201/0132 , B81C2201/014 , G01P15/0802 , G01P15/125 , G01P2015/0814 , Y10S148/012 , Y10S148/135 , Y10S148/159
Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole (20) dry etching of an element substrate (3), and an electrically conductive material is used as an etching stop layer (18) during the dry etching.
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255.发明授权MICROSTRUCTURES AND SINGLE MASK, SINGLE-CRYSTAL PROCESS FOR FABRICATION THEREOF 失效微结构和EINZELMASK，单晶制造方法
公开(公告)号：EP0683921B1
公开(公告)日：2004-06-16
申请号：EP94903348.4
申请日：1993-12-03
Applicant: CORNELL RESEARCH FOUNDATION, INC.
Inventor： SHAW, Kevin, A. , ZHANG, Z., Lisa , MACDONALD, Noel, C.
IPC: H01L21/44 , H01L21/449 , H01L21/302 , H01L23/48 , H01L29/06 , H01L29/86 , H01L29/84 , H01L29/96
CPC classification number: B81C1/00619 , B81C1/00142 , B81C1/0015 , B81C1/00626 , B81C2201/0112 , B81C2201/0132 , B81C2201/053 , G01P15/0802 , G01P15/125 , G01P2015/0814 , G01P2015/0817 , G01P2015/0828 , Y10S73/01 , Y10S148/05
Abstract: The invention provides a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation. A dielectric mask (12) on a single-crystal substrate (154) is patterned to define isolating trenches. A protective conformal layer (28) is applied to the resultant structure. The conformal layer (28) on the floor of the trenches is removed and a second etch deepens the trench to expose the mesa walls which are removed during the release step by isotropic etching. A metal layer (44) is formed on the resultant structure providing opposed plates (156) and (158) of a capacitor. The cantilever beam (52) with the supporting end wall (152) extends the grid-like structure (150) into the protection of the deepened isolation trenches (54). A membrane can be added to the released structures to increase their weight for use in accelerometers, and polished for use as movable mirrors.
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Patent Agency Ranking
公开(公告)号：EP1259980A1
公开(公告)日：2002-11-27
申请号：EP01913007.9
申请日：2001-02-22
Applicant: Applied Materials, Inc.
Inventor： KHAN, Anisul , KUMAR, Ajay , CHINN, Jeffrey, D. , PODLESNIK, Dragan
IPC: H01L21/3065
CPC classification number: H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89° +/-1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.
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公开(公告)号：KR20180059538A
公开(公告)日：2018-06-04
申请号：KR20187012304
申请日：2016-09-29
IPC: B81C1/00
CPC classification number: B81C1/00476 , B81B2201/033 , B81C1/00619 , B81C99/0095 , B81C2201/0132 , B81C2201/056
Abstract: 간소화된멤스소자의제조공정및 멤스소자가저렴하고경량의멤스소자의제조를가능하게하도록제공된다. 상기공정은상기멤스소자내에복수의홀이나다른형상패턴을식각하고난 후, 기저웨이퍼를식각제거하는것을포함함으로써, 식각공정후에추가의웨이퍼박화공정이나다이의다이싱공정을하지않고도, 상기멤스소자는요구되는두께가되고, 개별다이는분리된다. 상기기판웨이퍼내로트렌치를식각하고멤스기초재료로트렌치를채움으로써, 더큰 힘을갖고정교하며더 높은멤스소자가제조될수 있다.
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公开(公告)号：KR101609229B1
公开(公告)日：2016-04-20
申请号：KR1020137021344
申请日：2012-01-13
Applicant: 카벤디시 키네틱스, 인크.
Inventor： 르노,미카엘 , 레이시,조셉대미언고든 , 조쉬,비크람 , 맥과이어,토머스엘.
CPC classification number: B81B3/0072 , B81B2203/0118 , B81B2203/0307 , B81B2207/096 , B81C1/00039 , B81C1/00333 , B81C1/00476 , B81C2201/0132 , B81C2201/014 , B81C2203/0145 , B81C2203/0714
Abstract: 본발명은일반적으로 MEMS 또는 NEMS 디바이스를제조하는방법및 이디바이스에관한것이다. 캔틸레버구조체에비해더 낮은재결합계수를가지는물질의박막층은캔틸레버구조체, RF 전극및 풀오프전극위에증착될수 있다. 박막층은공동으로도입되는에칭가스로하여금공동내에전체에칭제재결합속도를감소시켜공동내에희생물질의에칭속도를증가시킬수 있게한다. 에칭제그 자체는희생물질의최상부층이제일먼저에칭되도록캔틸레버구조체의앵커부분과선형으로정렬된캡슐층 내개구를통해도입될수 있다. 이후밀봉물질이공동을밀봉할수 있고이 밀봉물질은공동을통해앵커부분으로연장하여앵커부분에추가적인강도를제공한다.
Abstract translation: 技术领域本发明总体上涉及用于制造MEMS或NEMS器件的方法和设备。 具有比悬臂结构上的下部重组系数的材料制成的薄膜层可以在悬臂结构，RF电极和池电极断开来沉积。 薄膜层使引入到空腔中，以降低整体蚀刻速率组合材料在空腔中使得它可以增加腔内的牺牲材料的蚀刻速率的蚀刻气体。 蚀刻AIGUES本身可以通过与悬臂结构的锚定部分线性对齐的开口内的胶囊型层被引入，使得首先蚀刻该牺牲材料的顶层。 然后密封材料可以密封空腔并且密封材料穿过空腔延伸到锚固部分以向锚固部分提供额外的强度。
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公开(公告)号：KR1020160037961A
公开(公告)日：2016-04-06
申请号：KR1020167004660
申请日：2014-07-23
Applicant: 쓰리엠 이노베이티브 프로퍼티즈 캄파니
CPC classification number: C23C16/0245 , B81C1/00031 , B81C2201/0132 , C09J7/22 , C09J2201/606 , C23C16/50 , H01J37/32082 , H01J37/32541 , H01J2237/3321 , H01J2237/3341
Abstract: 반응종으로기재의주 표면을에칭하면서사실상동시에가스상혼합물로부터플라즈마화학증착에의해표면에층을침착시킴으로써나노구조체를제조하는방법및 나노구조화물품. 본방법은기재를제공하는단계, 플라즈마로형성될때 기재상에층을침착시킬수 있는제1 가스종을, 플라즈마로형성될때 기재를에칭할수 있는제2 가스종과혼합하여, 가스상혼합물을형성하는단계, 가스상혼합물을플라즈마로형성하는단계, 및기재의표면을플라즈마에노출시켜 - 표면이에칭되고, 사실상동시에, 에칭된표면의적어도일부분상에층이침착되며 -, 그럼으로써나노구조체를형성하는단계를포함한다. 기재는 (공)중합체성재료, 무기재료, 합금, 고용체, 또는이들의조합일수 있다. 침착된층은유기규소화합물, 금속알킬화합물, 금속아이소프로폭사이드화합물, 금속아세틸아세토네이트화합물, 금속할로겐화물화합물, 및이들의조합으로이루어진군으로부터선택되는화합물을포함하는반응물가스를사용하는플라즈마화학증착의반응생성물을포함할수 있다. 고종횡비를갖고선택적으로적어도하나의치수에서, 그리고바람직하게는 3개의직교하는치수들에서랜덤한치수를갖는나노구조체가제조될수 있다.
Abstract translation: 一种通过从气体混合物的等离子体化学气相沉积而将基底沉积到基底的主表面上而形成纳米结构和纳米结构化制品的方法，同时基本上同时用反应性物质蚀刻该表面。 该方法包括提供基板; 当形成等离子体时，能够将能够沉积到衬底上的第一气态物质混合，当形成等离子体时，能够蚀刻衬底的第二气态物质，从而形成气态混合物; 将气态混合物形成等离子体; 以及将所述衬底的表面暴露于所述等离子体，其中所述表面被蚀刻并且基本上同时地在所述蚀刻表面的至少一部分上沉积层，从而形成所述纳米结构。 基底可以是（共）聚合物材料，无机材料，合金，固溶体或其组合。 沉积层可以包括使用包含选自有机硅化合物，金属烷基化合物，金属异丙醇化合物，金属乙酰丙酮化合物，金属卤化物化合物及其组合的化合物的反应气体的等离子体化学气相沉积的反应产物。 可以制备高纵横比的纳米结构，并且任选地在至少一个维度，优选三个正交尺寸的随机尺寸。
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公开(公告)号：KR1020150135287A
公开(公告)日：2015-12-02
申请号：KR1020157026106
申请日：2014-03-17
Applicant: 도쿄엘렉트론가부시키가이샤
CPC classification number: B81C1/00047 , B81C2201/0104 , B81C2201/0108 , B81C2201/0132 , B82Y40/00
Abstract: 오목형상을포함하는하부구조체(30)가준비되고, 증착중합법에의해, 상기하부구조체위에유기막으로이루어지는희생막(40)을퇴적시켜, 상기오목형상이상기희생막으로매립되고, 상기희생막의불필요부분이제거되고, 불필요부분이제거된상기희생막위에상부구조체(50)가형성되고, 상기희생막을제거하여, 상기하부구조체와상기상부구조체의사이에공극을형성함으로써, 중공구조체가제조된다.
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