公开(公告)号：WO2013137338A1

公开(公告)日：2013-09-19

申请号：PCT/JP2013/057055

申请日：2013-03-13

Applicant: コーア株式会社

Inventor： 豊田　素久 ,  前田　幸則 ,  唐澤　秀和 ,  有賀　克実

IPC: H01C1/14 ,  H01C17/28

CPC classification number: H01C1/148 ,  H01C7/003 ,  H01C17/006 ,  H01C17/281 ,  H05K1/0298 ,  H05K1/185 ,  H05K2201/097 ,  H05K2201/09945 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611

Abstract: 　抵抗器表裏面の両面にビア経由で配線接続が可能な基板内蔵用チップ抵抗器を提供する。絶縁性基板（１１）と、第１内部電極（１２）と、抵抗膜（１３）と、保護膜（１４）と、第１内部電極の露出部と接続され、前記保護膜の端部を覆うように形成された一対の第２内部電極（１５）と、基板の裏面に形成された、基板の表面に前記第１内部電極および前記第２内部電極により形成された内部電極と同じ大きさの第３内部電極（１６）と、基板の端面に形成された端面導電層（１７）と、基板の表面に形成された前記内部電極と、端面導電層と、基板の裏面に形成された第３内部電極を連続的に被覆する外部電極（１８）を備え、基板の表面に形成された前記内部電極および基板の裏面に形成された第３内部電極は、基板の長手方向長さの１／３以上で１／２未満である。

Abstract translation: 提供了一种芯片电阻器，其被并入到基板中并且能够通过电阻器的前表面和后表面上的通孔进行布线连接。 芯片电阻器设置有：绝缘基板（11）; 第一内部电极（12）; 电阻膜（13）; 保护膜（14）; 形成为覆盖保护膜的端部并与第一内部电极的露出部分连接的一对第二内部电极（15） 第三内部电极（16），形成在所述基板的后表面上，并且具有与形成在所述基板的前表面上的所述第一和第二内部电极的所述内部电极相同的尺寸; 形成在所述基板的端面上的端面导电层（17） 以及用于连续地覆盖形成在基板的表面上的内部电极的外部电极（18），端面导电层和形成在基板的后表面上的第三内部电极。 其中，形成在基板的前表面上的内部电极和形成在基板的后表面上的第三内部电极的长度方向上的基板的长度为基板的长度的1/3以上且小于1/2。

公开(公告)号：WO2009045888A2

公开(公告)日：2009-04-09

申请号：PCT/US2008/077830

申请日：2008-09-26

Applicant: ACCESS BUSINESS GROUP INTERNATIONAL LLC ,  BAARMAN, David, W. ,  SCHWANNECKE, Joshua, K. ,  GUTHRIE, Warren, E. ,  WAHL, Richard, A. ,  DUCKWORTH, Paul

Inventor： BAARMAN, David, W. ,  SCHWANNECKE, Joshua, K. ,  GUTHRIE, Warren, E. ,  WAHL, Richard, A. ,  DUCKWORTH, Paul

IPC: H05K1/16

CPC classification number: H05K1/165 ,  H01F5/003 ,  H05K1/0228 ,  H05K2201/097

Abstract: A multilayer printed circuit board ("PCB") coil that simulates a coil formed from litz wire. The PCB includes a plurality of alternating conductor and insulating layers interconnected to cooperatively form the coil. Each conductor layer includes a trace that follows the desired coil shape and is divided into a plurality of discrete conductor segments. The segments are electrically connected across layers to provide a plurality of current flow paths (or filaments) that undulate between the layers in a regular, repeating pattern. The coil may be configured so that each filament spends a substantially equal amount of time in proximity to the paired coil and therefore contributes substantially equally to the self or mutual inductance of the coil. Each conductor layer may include a plurality of associated traces and intralayer connector that interconnected so that each filament undulates not only upwardly/downwardly, but also inwardly/outwardly in a regular, repeating pattern.

Abstract translation: 一种模拟由绞合线形成的线圈的多层印刷电路板（“PCB”）线圈。 PCB包括多个交替的导体和绝缘层，互连以协作地形成线圈。 每个导体层包括跟随期望的线圈形状的迹线，并被分成多个分立的导体段。 这些片段跨层电连接以提供以规则的重复图案在层之间起伏的多个电流流动路径（或细丝）。 线圈可以被配置成使得每个灯丝在接近成对的线圈处花费大致相等的时间量，并且因此基本上等同于线圈的自相互作用或互感。 每个导体层可以包括多个相关联的迹线和层内连接器，其互连，使得每个细丝不仅向上/向下而且以规则的重复图案向内/向外波动。

公开(公告)号：WO2008057717B1

公开(公告)日：2008-09-18

申请号：PCT/US2007081343

申请日：2007-10-15

Applicant: MOTOROLA INC ,  MAGERA JAROSLAW A ,  DUNN GREGORY J ,  LEGANSKI KATHY D

Inventor： MAGERA JAROSLAW A ,  DUNN GREGORY J ,  LEGANSKI KATHY D

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/427 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49165

Abstract: A method for forming closed vies In a mgtfflayßr printed circuit board. A dielectric layer Is laminated to one side of a central. core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vtas In the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that Is much smaller In diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hols. Approximately one half of the closed vlas are situated such that the closed aperture faces one dielectric layer and a remainder of the dosed vias are situated such that the closed aperture faces the other dielectric layer.

Abstract translation: 一种形成封闭的威胁的方法在一个mgtfflayßr印刷电路板中。 介电层被层压到中心的一侧。 芯在每侧具有金属层。 第二电介质层被层压到中心芯的另一侧。 封闭的Vtas中心芯是通过部分穿过但不完全穿透中心芯而形成的，然后从相对侧完成通孔，该孔的直径要小得多，以形成完全穿透中心芯的通道 从一边到另一边。 然后通孔用金属镀以基本上封闭较小的霍尔。 大约一半的闭合孔被定位成使得闭合孔面对一个电介质层，并且其余的经过定型的通孔被设置成使得闭合孔面对另一介电层。

公开(公告)号：WO2006086177A1

公开(公告)日：2006-08-17

申请号：PCT/US2006/003256

申请日：2006-01-30

Applicant: NORTHROP GRUMMAN CORPORATION ,  WINTER, Frank, B. ,  HARBERTS, Harry, S. ,  TOLAN, Julius, G.

Inventor： WINTER, Frank, B. ,  HARBERTS, Harry, S. ,  TOLAN, Julius, G.

IPC: H05K1/16 ,  H01F17/00

CPC classification number: H01F17/0033 ,  H01F41/041 ,  H01F2017/002 ,  H05K1/165 ,  H05K2201/097 ,  Y10T29/4902

Abstract: A highly compact inductor formed on opposite faces of a dielectric substrate. Sets of parallel spaced conductive traces formed on the opposite faces of the substrate are interconnected by metallized vias through the substrate, in such a way as to form a continuous spiral conductive path. The inductor is preferably formed as two closely adjacent segments, each with conductive traces on each face of the substrate and each having metallized vias interconnecting the conductive traces. The segments are electrically connected in series and produce a magnetic field that extends through each segment in opposite directions and is closely coupled from one segment to the other. The inductor is, therefore, electromagnetically similar to a wire-wound toroidal inductor, providing high inductance and contourable Q values, but is highly compact, especially in the z-axis direction normal to the substrate.

Abstract translation: 形成在电介质基板的相对面上的高度紧凑的电感器。 在衬底的相对表面上形成的平行间隔的导电迹线的集合通过穿过衬底的金属化通孔互连，以形成连续的螺旋形导电路径。 电感器优选地形成为两个紧密相邻的段，每个具有在衬底的每个表面上的导电迹线，并且每个具有互连导电迹线的金属化通孔。 这些段串联电连接并且产生一个磁场，该磁场沿相反方向延伸穿过每个段，并且从一个段紧密耦合到另一个段。 因此，电感器电磁地类似于绕线环形电感器，提供高电感和可轮廓的Q值，但是非常紧凑，特别是在垂直于衬底的z轴方向上。

公开(公告)号：WO2006063081A2

公开(公告)日：2006-06-15

申请号：PCT/US2005/044319

申请日：2005-12-07

Applicant: M-FLEX MULTI-FINELINE ELECTRONIX, INC. ,  WHITTAKER, Ronald W. ,  GUERRA, Joe D. ,  MARCOCI, Ciprian

Inventor： WHITTAKER, Ronald W. ,  GUERRA, Joe D. ,  MARCOCI, Ciprian

IPC: H01F5/00

CPC classification number: H01F27/266 ,  H01F17/0033 ,  H01F17/062 ,  H01F19/04 ,  H01F27/2804 ,  H01F41/046 ,  H01F2017/002 ,  H05K1/165 ,  H05K1/189 ,  H05K3/389 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10416 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Electrical connection between the plural levels of circuitry and multiple windings around magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.

Abstract translation: 微型电路和电感器部件，其中在支撑面板的每一侧，通常是印刷电路板或刚性柔性件上形成多层印刷电路。 多层电路和磁性构件周围的多个绕组之间的电连接由多个电镀通孔导体提供。 小的通孔开口容纳多个电镀通孔导体，因为它们通过非常薄的真空沉积的有机层（例如具有高介电强度的聚对二甲苯）绝缘。 通过首先在有机层的表面上施加粘合剂促进剂，然后真空沉积有机层来提供该镀铜的有机层的附着力。

公开(公告)号：WO2006020488A1

公开(公告)日：2006-02-23

申请号：PCT/US2005/027748

申请日：2005-08-02

Applicant: TESSERA, INC. ,  HABA, Belgacem ,  BEROZ, Masud ,  TUCKERMAN, David B. ,  HUMPSTON, Giles ,  CRISP, Richard D.

Inventor： HABA, Belgacem ,  BEROZ, Masud ,  TUCKERMAN, David B. ,  HUMPSTON, Giles ,  CRISP, Richard D.

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/041 ,  H05K3/06 ,  H05K3/202 ,  H05K3/4038 ,  H05K2201/09609 ,  H05K2201/097 ,  H05K2201/09827 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate (10) is included having opposing surfaces and a plurality of holes (12A-D) extending through the surfaces. Also included is a plurality of electrically conductive posts (18A-D). Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate (20) may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts (28A-D) may be provided having tips in corresponding holes (22A-D) of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.

Abstract translation: 提供了用于微电子器件的连接结构和用于形成结构的方法。 包括具有相对表面的基板（10）和延伸穿过表面的多个孔（12A-D）。 还包括多个导电柱（18A-D）。 每个柱从基部延伸到位于基板的相应孔内的尖端。 可以设置另外的基板（20），使得每个柱的基部位于其表面上。 可以在附加基板的相应孔（22A-D）中提供附加的导电柱（28A-D）。 可选地，介电材料可以放置在基板和柱之间。

公开(公告)号：WO2004034756A3

公开(公告)日：2004-05-27

申请号：PCT/DK0300630

申请日：2003-09-25

Applicant: OTICON AS ,  MEHR ULRIK ,  JOHANSEN JESPER B

Inventor： MEHR ULRIK ,  JOHANSEN JESPER B

IPC: A61N1/04 ,  A61N1/16 ,  H05K1/00 ,  H05K1/02

CPC classification number: A61N1/16 ,  A61N1/04 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/0393 ,  H05K2201/097

Abstract: Layered structure for a head worn device, wherein electric signals are fed along metallic leads, which are adhered to a layer on or within the layered structure and where a first and a second lead for connecting a first and a second terminal of a component are provided and whereby the two leads are passed side by side and alternating on the two sides of the layer, and in such a manner that the first and second lead will cross one another at an angle but passing on each their side of the print layer.

Abstract translation: 用于头戴式设备的分层结构，其中电信号沿着金属引线馈送，金属引线粘附到分层结构上或层内的层，并且其中提供用于连接部件的第一和第二端子的第一和第二引线 并且由此两条引线并排并且在层的两侧交替穿过，并且以这样的方式使得第一引线和第二引线将以一定角度彼此交叉但是在印刷层的每一侧上通过。

公开(公告)号：WO2003100903A2

公开(公告)日：2003-12-04

申请号：PCT/US2003/016880

申请日：2003-05-28

Applicant: DECORP AMERICAS, INC. ,  SEXTON, Robert, J. ,  McCURDY, Michael, W. ,  MURRAY, David ,  POTTER, James, M. ,  WALLING, Linda, Sue

Inventor： SEXTON, Robert, J. ,  McCURDY, Michael, W. ,  MURRAY, David ,  POTTER, James, M. ,  WALLING, Linda, Sue

IPC: H01P

CPC classification number: H01P3/02 ,  H01P3/023 ,  H01P3/088 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0245 ,  H05K2201/09263 ,  H05K2201/097 ,  H05K2201/09727

Abstract: A non-uniform transmission line includes at least one patterned conductive layer, a dielectric layer adjacent to the patterned conductive layer(s), and an insulating layer surrounding the patterned conductive layer(s) and the dielectric layer.

Abstract translation: 非均匀传输线包括至少一个图案化导电层，与图案化导电层相邻的电介质层，以及围绕图案化导电层和电介质层的绝缘层。

公开(公告)号：WO2002060086A1

公开(公告)日：2002-08-01

申请号：PCT/US2001/050873

申请日：2001-10-29

Applicant: INTEL CORPORATION

Inventor： AMIRTHARAJAH, Rajeevan ,  BENHAM, John ,  MARKETKAR, Nandu

IPC: H04B5/00

CPC classification number: H01P5/185 ,  H01P5/187 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0239 ,  H05K1/0245 ,  H05K1/14 ,  H05K2201/09263 ,  H05K2201/097

Abstract: An electromagnetic (EM) coupler including a first transmission structure having a first geometry, and a second transmission structure having a second geometry and forming an EM coupler with the first transmission structure, the first and second geometries being selected to reduce sensitivity of EM coupling to relative positions of the first and second transmission structures is disclosed.

Abstract translation: 包括具有第一几何形状的第一传输结构和具有第二几何形状的第二传输结构并且形成具有第一传输结构的EM耦合器的电磁（EM）耦合器，选择第一和第二几何形状以降低EM耦合到 公开了第一和第二传输结构的相对位置。

公开(公告)号：WO0232198A3

公开(公告)日：2002-06-13

申请号：PCT/US0131457

申请日：2001-10-09

Applicant: PRIMARION INC

Inventor： DUFFY THOMAS P

IPC: H01F17/00 ,  H01F17/06 ,  H01F41/04 ,  H05K1/16 ,  H05K3/06

CPC classification number: H01F17/0033 ,  H01F17/06 ,  H01F41/046 ,  H05K1/165 ,  H05K3/06 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/10689 ,  Y10T29/4902 ,  Y10T29/49075 ,  Y10T29/49165

Abstract: An improved magnetic structure suitable for electronic applications is disclosed. The magnetic structure (304, 306) may be formed on or within a substrate (302) such as a printed circuit board by forming a layer of magnetic material, pattering the layer of magnetic material, and etching the layer to form the magnetic structure. Various insulating layers (310-316) and/or conductive layers (318-368) may then be formed over the magnetic structures as part of the substrate. Inductors suitable for use in power supplies may be formed using the magnetic structures of the present invention.

Abstract translation: 公开了一种适用于电子应用的改进的磁结构。 磁性结构（304,306）可以通过形成磁性材料层，图案化的磁性材料层，以及蚀刻该层以形成磁性结构，形成在诸如印刷电路板的衬底（302）之上或之内。 然后可以在作为衬底的一部分的磁性结构上形成各种绝缘层（310-316）和/或导电层（318-368）。 可以使用本发明的磁性结构形成适用于电源的电感器。