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21.发明公开AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT 有权FOR BIT SERIAL FIR，IIR滤波器和组合/顺序逻辑结构无延迟系数建筑面积高效生产
公开(公告)号：EP1119909A1
公开(公告)日：2001-08-01
申请号：EP98950601.9
申请日：1998-10-13
Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics Limited
Inventor： MALIK, Rakesh,STMicroelectronics Limited , GOEL, Puneet
IPC: H03H17/02
CPC classification number: H03H17/0225
Abstract: The invention relates to area efficient realization of coefficient block [A] or architecture [A] with hardware sharing techniques and optimizations applied to this block. The block [A] is connected to coefficient lines CLin_0, CLin_1...CLin_n and BLin_0, BLin_1,... BLin_n coming from block [E] and/or [F], to be connected to perform filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The invention also gives the area minimal realization of digital filters based on coefficient block [A], when operated in bit serial fashion. The optimization techniques and structure of the present invention are good for linear digital filters typically a finite impulse response (FIR) filter, infinite impulse response filter (IIR) and for other filters and applications based on combinational logic consisting of delay element (T), multiplier (M), adder (SA) and subtractor (SS).
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公开(公告)号：EP0666636B1
公开(公告)日：1999-09-15
申请号：EP95300265.6
申请日：1995-01-17
Applicant: STMicroelectronics Pte Ltd.
IPC: H02M1/10
CPC classification number: H02M1/10
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公开(公告)号：EP4362071A3
公开(公告)日：2024-09-25
申请号：EP23206096.2
申请日：2023-10-26
Applicant: STMicroelectronics Pte Ltd.
Inventor： GANI, David
IPC: H01L21/60 , H01L23/538 , H01L21/683 , H01L21/56 , H01L23/31
CPC classification number: H01L24/19 , H01L23/5389 , H01L23/3128 , H01L21/561 , H01L21/568 , H01L24/97 , H01L21/6835 , H01L2221/6834520130101
Abstract: The present disclosure is directed to at least one semiconductor package including a die (204) within an encapsulant (202) having a first sidewall, an adhesive layer (222) on the encapsulant and having a second sidewall coplanar with the first sidewall of the encapsulant, and an insulating layer (226) on the adhesive layer having a third sidewall coplanar with the first sidewall and the second sidewall. A method of manufacturing the at least one semiconductor package includes forming an insulating layer on a temporary adhesion layer of a carrier, forming an adhesive layer on the insulating layer, and forming a plurality of openings through the adhesive layer and the insulating layer. The plurality of openings through the adhesive layer and the insulating layer may be formed by exposing the adhesive layer and the insulating layer to a laser.
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24.发明公开IMPROVED VACUUM INTEGRATED ELECTRONIC DEVICE AND MANUFACTURING PROCESS THEREOF 审中-公开改进的真空集成电子器件及其制造工艺
公开(公告)号：EP3171387A1
公开(公告)日：2017-05-24
申请号：EP16194697.5
申请日：2016-10-19
Applicant: STMicroelectronics S.r.l. , STMicroelectronics Pte Ltd.
Inventor： PATTI, Davide Giuseppe , KIM, Myung Sung
CPC classification number: H01J19/02 , H01J9/025 , H01J9/18 , H01J21/04 , H01J21/105 , H01J21/20 , H01J2209/012 , H01J2209/02
Abstract: A vacuum integrated electronic device (120) has an anode region (101) of conductive material; an insulating region (102, 104) on top of the anode region; a cavity (54) extending through the insulating region and having a sidewall (53); and a cathode region (109). The cathode region has a tip portion (51, 52) extending peripherally within the cavity, adjacent to the sidewall of the cavity. The cathode region is formed by tilted deposition, carried out at an angle of 30-60° with respect to a perpendicular to the surface of device.
Abstract translation: 真空集成电子器件（120）具有导电材料的阳极区域（101） 在所述阳极区域的顶部上的绝缘区域（102,104） 延伸穿过绝缘区域并具有侧壁（53）的空腔（54）; 和阴极区（109）。 阴极区具有在空腔内沿周边延伸的邻近空腔侧壁的尖端部分（51,52）。 阴极区域通过倾斜沉积形成，相对于器件表面的垂线以30-60°的角度进行。
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25.发明公开Via-less thin film resistor with a dielectric cap and manufacturing method thereof 审中-公开而不接触孔薄膜电阻器与它们的电介质层及其制造方法
公开(公告)号：EP2423950A3
公开(公告)日：2013-05-01
申请号：EP11178597.8
申请日：2011-08-24
Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics, Inc.
Inventor： Lim, Ting Fang , Niu, Chengyu , Le Neel, Olivier , Leung, Calvin
IPC: H01L49/02 , H01L23/522 , H01L23/64 , H01L21/768 , H01C7/00
Abstract: The present disclosure is directed to a thin film resistor structure (100) that includes a resistive element (102) electrically connecting first conductor layers (106a,b) of adjacent interconnect structures (104a,b). The resistive element is covered by a dielectric cap layer (105) that acts as a stabilizer and heat sink for the resistive element. Each interconnect includes a second conductor layer (124) over the first conductive layer. The thin film resistor includes a chromium silicon resistive element covered by a silicon nitride cap layer.
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Patent Agency Ranking26.发明公开
公开(公告)号：EP2423949A3
公开(公告)日：2013-05-01
申请号：EP11178593.7
申请日：2011-08-24
Applicant: STMicroelectronics Pte Ltd.
Inventor： Le Neel, Olivier , Leng, Calvin
IPC: H01L49/02 , H01L23/522 , H01L21/768
CPC classification number: H01L23/5228 , H01L21/76834 , H01L21/76852 , H01L28/20 , H01L28/24 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
Abstract: The present disclosure is directed to a thin film resistor (102) having a first resistor layer (103a) having a first temperature coefficient of resistance and a second resistor layer (103b) on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 5-15 nm and the second resistor layer may have a thickness in the range of 2-5 nm.
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27.发明公开Via-less thin film resistor with a dielectric cap and manufacturing method thereof 审中-公开而不接触孔薄膜电阻器与它们的电介质层及其制造方法
公开(公告)号：EP2423950A2
公开(公告)日：2012-02-29
申请号：EP11178597.8
申请日：2011-08-24
Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics Inc
Inventor： Lim, Ting Fang , Niu, Chengyu , Le Neel, Olivier , Leung, Calvin
IPC: H01L21/02 , H01L23/522 , H01L23/64
Abstract: The present disclosure is directed to a thin film resistor structure (100) that includes a resistive element (102) electrically connecting first conductor layers (106a,b) of adjacent interconnect structures (104a,b). The resistive element is covered by a dielectric cap layer (105) that acts as a stabilizer and heat sink for the resistive element. Each interconnect includes a second conductor layer (124) over the first conductive layer. The thin film resistor includes a chromium silicon resistive element covered by a silicon nitride cap layer.
Abstract translation: 本发明涉及的薄膜电阻器结构（100）包括一电阻性元件那样（102），其电连接第一导体层（106A，B）相邻的互连结构（104A，B）。 所述电阻元件由介电覆盖层覆盖（105）确实用作稳定剂和散热器为电阻元件。 每个互连件包括在所述第一导电层的第二导体层（124）。 薄膜电阻器包括由硅氮化物帽层覆盖的硅铬电阻元件。
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公开(公告)号：EP1298935A3
公开(公告)日：2010-09-22
申请号：EP02292260.3
申请日：2002-09-16
Applicant: STMicroelectronics S.A. , Groupe des Ecoles des Telecommunications , STMicroelectronics Pte Ltd.
Inventor： Bard, Jean-Michel , Danger, Jean-Luc , Hui, Lucas , Cunat, Christophe
CPC classification number: H04N19/436 , H04N19/126 , H04N19/152 , H04N19/176 , H04N19/194 , H04N19/196 , H04N19/197 , H04N19/60
Abstract: Procédé de compression d'un signal d'image numérique dans lequel un premier jeu de pas de quantification, unique pour un segment donné, est déterminé pour que le nombre de bits nécessaires pour coder les données quantifiées correspondant à ce segment soit supérieur à une valeur cible. Ce premier jeu de pas de quantification étant ensuite modifié, en priorité, pour les blocs du segment pour lesquels le gain, au cours de cette modification, sur la réduction du nombre de bits nécessaires pour coder les données quantifiées correspondant au segment auquel il appartient, est le plus élevé. Cette modification est effectuée, sur autant de blocs qu'il est nécessaire pour que le nombre de bits de ce segment soit inférieur ou égal à la valeur cible.
Dispositif pour la mise en oeuvre de ce procédé.-
29.发明授权AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT 有权FOR BIT SERIAL FIR，IIR滤波器和组合/顺序逻辑结构无延迟系数建筑面积高效生产
公开(公告)号：EP1119910B1
公开(公告)日：2004-01-14
申请号：EP98950602.7
申请日：1998-10-13
Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics Limited
Inventor： MALIK, Rakesh-STMicroelectronics Limited , GOEL, Puneet
IPC: H03H17/02
CPC classification number: H03H17/0223 , H03H17/0225 , H03H17/0227 , H03H2218/08 , H03H2218/10
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30.发明授权AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT 有权FOR BIT SERIAL FIR，IIR滤波器和组合/顺序逻辑结构无延迟系数建筑面积高效生产
公开(公告)号：EP1119909B1
公开(公告)日：2004-01-14
申请号：EP98950601.9
申请日：1998-10-13
Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics Limited
IPC: H03H17/02
CPC classification number: H03H17/0225
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