公开(公告)号：US20240347593A1

公开(公告)日：2024-10-17

申请号：US18292584

申请日：2022-02-17

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A nanowire/nanosheet device and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device. The nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; a source/drain layer at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; a gate stack extending in a second direction intersecting with the first direction to surround the nanowire/nanosheet; and a first spacer on a sidewall of the gate stack, wherein the first spacer includes a continuously extending material layer which has a first part along a surface of the nanowire/nanosheet, a second part along a sidewall of the source/drain layer facing the gate stack, and a third part along a sidewall of the gate stack facing the source/drain layer, and the second part and the third part have a seam or an interface therebetween.

公开(公告)号：US12096623B2

公开(公告)日：2024-09-17

申请号：US17309775

申请日：2019-04-09

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Weixing Huang ,  Kunpeng Jia

IPC: H10B41/27 ,  H01L29/423 ,  H01L29/788

CPC classification number: H10B41/27 ,  H01L29/42324 ,  H01L29/788

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

公开(公告)号：US20240305479A1

公开(公告)日：2024-09-12

申请号：US17756314

申请日：2021-04-19

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Feng ZHANG ,  Yiming WANG ,  Qirui REN

IPC: H04L9/32 ,  H04L9/08

CPC classification number: H04L9/3278 ,  H04L9/0869 ,  H04L2209/12

Abstract: An encryption method includes: receiving cipher data which is binary data; determining target components in a resistive memory array according to values of respective bits in the cipher data; determining current values generated by respective columns of components according to the target components; and generating key data according to the current values generated by the respective columns of components. The present disclosure can effectively reduce computing power and power consumption of an encryption process in an edge device.

公开(公告)号：US20240292618A1

公开(公告)日：2024-08-29

申请号：US18547391

申请日：2023-04-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H10B43/27 ,  H10B51/20

CPC classification number: H10B43/27 ,  H10B51/20

Abstract: Disclosed are a memory device, a method of manufacturing the memory device, and an electronic device. The memory device may include: a plurality of first device layers, each including first and second source/drain regions and a channel region; a plurality of second device layers stacked on the first device layers, each including third and fourth source/drain regions and a channel region; and a gate stack extending vertically to pass through the first and second device layers. The gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and each device layer, and a memory cell is defined at an intersection of the gate stack and each device layer. The gate stack has a surface in a bended shape at a position where the plurality of first device layers are adjacent to the plurality of second device layers.

公开(公告)号：US12046672B2

公开(公告)日：2024-07-23

申请号：US17112739

申请日：2020-12-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/2254 ,  H01L21/28114 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66666

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device may include: a substrate; a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other, and a gate stack formed around an outer periphery of the channel region; wherein the gate stack has a thickness varying in a direction perpendicular to a top surface of the substrate.

公开(公告)号：US20240194598A1

公开(公告)日：2024-06-13

申请号：US18532246

申请日：2023-12-07

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jianfeng GAO ,  Weibing LIU ,  Junjie LI ,  Na ZHOU ,  Tao YANG ,  Junfeng LI ,  Jun LUO

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226

Abstract: A metal interconnection structure of a semiconductor device and a method for forming the same. The method includes: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive structure in the first dielectric layer; etching back part of the first conductive structure; forming an etch stop layer on the first conductive structure; forming a second dielectric layer on the etch stop layer and performing chemical mechanical polishing; and forming a second conductive structure in the second dielectric layer, where the second conductive structure is electrically connected to the first conductive structure.

公开(公告)号：US12002500B2

公开(公告)日：2024-06-04

申请号：US17426053

申请日：2019-01-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing Lv ,  Qing Luo ,  Xiaoxin Xu ,  Tiancheng Gong ,  Ming Liu

IPC: G11C11/22 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C16/14 ,  G11C16/3404

Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

公开(公告)号：US20240147686A1

公开(公告)日：2024-05-02

申请号：US17770856

申请日：2021-12-09

Applicant: Beijing Superstring Academy of Memory Technology ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qi WANG ,  Huilong ZHU

IPC: H10B12/00 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B12/00 ,  H01L29/6675 ,  H01L29/78645 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention relates to a semiconductor memory cell structure, a semiconductor memory as well as preparation method and application thereof. The semiconductor memory cell structure includes: a substrate; and a first transistor layer, an isolation layer and a second transistor layer. The first transistor layer includes a first stack structure formed by stacking a first source, a first channel, and a first drain from bottom to top; and a first gate located on a sidewall of the first stack structure. The second transistor layer includes: a second stack structure formed by stacking a second drain, a second channel, and a second source from bottom to top; and a second gate located on a sidewall of the second stack structure, at least a part of a sidewall of the second drain is in direct contact with the first gate. The present invention provides a 2T0C type DRAM cell with an improved structure, has the advantages of vertical stack integration, high integration level, low leakage current, short refresh time and the like, and is significantly superior to the existing 2T0C type DRAM.

公开(公告)号：US20240130251A1

公开(公告)日：2024-04-18

申请号：US18277977

申请日：2022-03-10

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Xiaoxin XU ,  Wenxuan SUN ,  Jie YU ,  Woyu ZHANG ,  Danian DONG ,  Jinru LAI ,  Xu ZHENG ,  Dashan SHANG

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/20 ,  H10B63/845 ,  H10N70/011

Abstract: A three-dimensional reservoir based on three-dimensional volatile memristors and a method for manufacturing the same. In the three-dimensional reservoir, a memory layer, a select layer, and an electrode layer in each via form a memristor which is a reservoir unit. The three-dimensional reservoir is formed based on a stacking structure and multiple vias. The three-dimensional reservoir is constructed by using virtual nodes generated from dynamic characteristics of the three-dimensional memristors. An interfacial memristor is first constructed, and its volatility is verified through electric tests. A vertical three-dimensional array is manufactured based on the volatile memristor. A dynamic characteristic of the memristor is adjusted through a Schottky barrier. Different layers in the three-dimensional reservoir correspond to different reservoirs, which are constructed by controlling memristors in the different layers, respectively.

公开(公告)号：US11961787B2

公开(公告)日：2024-04-16

申请号：US17545676

申请日：2021-12-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L23/528

Abstract: A semiconductor device with a sidewall interconnection structure and a method for manufacturing the same, and an electronic apparatus including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a vertical stack including a plurality of element layers, wherein each element layer of the plurality of element layers includes a plurality of semiconductor elements and a metallization layer for the plurality of semiconductor elements; and an interconnection structure laterally adjoined the vertical stack. The interconnection structure includes: an electrical isolation layer; and a conductive structure in the electrical isolation layer, wherein at least a part of a conductive structure in the metallization layer of the each element layer is in contact with and electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.