公开(公告)号：JPH022236A

公开(公告)日：1990-01-08

申请号：JP30046188

申请日：1988-11-28

Applicant: TANDEM COMPUTERS INC

Inventor： MAATEIN DABURIYUU SANAA

IPC: G06F1/12 ,  H03K5/00 ,  H03K5/135 ,  H04L7/02

Abstract: PURPOSE: To synchronize the rise of an input signal with the transition of a clock signal within one period of a clock signal at maximum by providing the two-step type synchronizing device with a pair of flip flops(FFs) constituted to write an input signal at the time of transition of a periodical pulse string to a positive pole or a negative pole. CONSTITUTION: At the time of transition of a CLK signal to the positive pole, an FF 12 writes an IN signal, and at the time of transition of the CLK signal to the negative pole, an FF 14 writes an IN signal. Output signals from the FFs 12, 14 are inputted to an OR gate 20 and respectively transmitted to the data(D) input terminals of FFs 16, 18. All of three output signals O1 to O3 form the display format of the IN signal synchronized with the transition of the CLK signal. Similar analysis can be applied also to the transition of the IN signal to the negative pole.

公开(公告)号：JPS6438980A

公开(公告)日：1989-02-09

申请号：JP9537588

申请日：1988-04-18

Applicant: TANDEM COMPUTERS INC

Inventor： EI RICHIYAADO ZATSUCHIYAA ,  JIEI AARIN ZUWAGAAMAN ,  FURANSHISU JIEI DOWAN

IPC: G06F13/40 ,  G11C5/00 ,  H01R13/64 ,  H01R13/70 ,  H05K7/14

Abstract: PURPOSE: To prevent the increase in power of a pair of modules mutually connected, when they are not electrically compatible by providing a means for connecting a control terminal only when modules are electrically compatible, and a switch capable of controlling the power to the module pair only when the control terminals is connected. CONSTITUTION: A first module 10 comprises a controllable switch 40, having two control terminals 42, 44, and supplies a power to a pair of modules 10, 12 mutually connected only when the two terminals 42, 44 are connected conductivley. When the electrically compatible modules 10, 12 are mutually connected, the control terminals 42, 44 are conductively connected to supply the power to the modules 10, 12. If the mutually connected modules 10, 12 are not compatible, the control terminals 42, 44 are not conductivity connected to interrupt the power supply to the modules 10, 12. Thus, arc discharge or data extinguishement can be prevented during the mutual connection.

公开(公告)号：JPS63273134A

公开(公告)日：1988-11-10

申请号：JP8708288

申请日：1988-04-08

Applicant: TANDEM COMPUTERS INC

Inventor： DANIERU II RENOOSUKI

IPC: G06F9/28 ,  G06F9/22 ,  G06F9/318 ,  G06F9/38

Abstract: A method and mechanism for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.

公开(公告)号：JPS62236038A

公开(公告)日：1987-10-16

申请号：JP7392887

申请日：1987-03-27

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  SHIRIRO RINO KOSUTANCHINO

IPC: G06F9/22 ,  G06F9/28 ,  G06F12/06 ,  G06F12/16 ,  G11C29/00

公开(公告)号：JPS6231440A

公开(公告)日：1987-02-10

申请号：JP10652786

申请日：1986-05-09

Applicant: TANDEM COMPUTERS INC

Inventor： CHANDRAN SRIKUMAR R ,  WALKER MARK S

IPC: G06F11/18 ,  G06F1/04 ,  G06F1/12 ,  H03K5/00 ,  H03K5/135 ,  H03K5/151

公开(公告)号：JPS61286962A

公开(公告)日：1986-12-17

申请号：JP13587486

申请日：1986-06-11

Applicant: TANDEM COMPUTERS INC

Inventor： JIEEMUSU AREN KATSUTSUMAN ,  JIYOERU FUORUSOMU BAATORETSUTO ,  RICHIYAADO MATSUKU KUROUDO BIK ,  UIRIAMU HENRII DEIBITSUDOO ,  JIYON AREKISANDAA DESUPOTAKISU ,  PIITAA JIYON GURAJIANO ,  MITSUCHIERU DENISU GURIIN ,  DEBITSUDO ARUBAATO GUREIGU ,  SUCHIIBUN JIYON HAYASHI ,  DEBITSUDO ROBAATO MATSUKII ,  DENISU REO MATSUKU EBOI ,  JIEEMUZU GARII TORAIBITSUGU ,  SUCHIIBUN UOOREN BUIERENGA

IPC: G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173

公开(公告)号：JPH1153302A

公开(公告)日：1999-02-26

申请号：JP14706898

申请日：1998-05-28

Applicant: TANDEM COMPUTERS INC

Inventor： RAHMAN MIZANUR M ,  SABERNICK FRED C ,  SPROUSE JEFF A ,  GROSZ MARTIN J ,  FU PETER ,  RECTOR RUSSELL M

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F15/16 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To improve an interface to a microprocessor by preparing a logic for intelligently limiting the flow of interrupt information passing through a processor bus between the microprocessor and a processor interface chip. SOLUTION: An interrupt filter 198 is connected to an internal bus interface 182 and a processor bus interface 180 and receives an interrupt signal from an internal bus 26 to send the interrupt given from a 1st class to a processor bus and to store the interrupt given from a 2nd class respectively. The interrupt of the 1st class gives a current effect to a flow of programs of a microprocessor. Meanwhile, the interrupt of the 2nd class gives no effect at all on the current flow of the programs before the stored interrupt affects the flow of the programs.

公开(公告)号：JPH1115687A

公开(公告)日：1999-01-22

申请号：JP14706598

申请日：1998-05-28

Applicant: TANDEM COMPUTERS INC

Inventor： RAHMAN MIZANUR M ,  SABERNICK FRED C ,  SPROUSE JEFF A ,  GROSZ MARTIN J ,  FU PETER ,  RECTOR RUSSELL M

IPC: G06F15/177 ,  G06F9/445 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F12/02 ,  G06F12/08 ,  G06F13/24 ,  G06F13/36 ,  G06F15/16 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To obtain an improved interface with respect to a microprocessor by providing a specific address preventing means and an address replacing means. SOLUTION: A boot address locator 194 is provided with a bus input, a bus output and an input for indicating whether the contents of a bus are addresses to be outputted to Ibus. When the contents of a bus are not addresses to be outputted to Ibus, data is put through to the locator 194 without changing data. An AND gate 400 is provided with two inputs, one of them is from a boot exception vector indicator register (BEV-PIC) 218 and the other is an input for indicating whether an input is an address to Ibus. When both of them are true, the AND gate 400 outputs a logic 1 (SELECT = 1) to the selective input of a multiplexer (1...6) to generate the relocation of the address of the bus.

公开(公告)号：JPH10307732A

公开(公告)日：1998-11-17

申请号：JP2997196

申请日：1996-01-23

Applicant: TANDEM COMPUTERS INC

Inventor： FISHLER LEONARD R ,  CLARK THOMAS M

IPC: G06F9/54 ,  G06F11/14 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To increase data transmission efficiency among various processes and between the processes and a driver by providing a common memory part in a memory and allowing the same processor to transmit data by a common memory queue matrix system without copying it each time the data is transmitted. SOLUTION: The memory 112 includes a software process 120, a software disk process 120, a software disk process 122 and the common memory part 124, and the common memory part 124 includes a queue 125. The processes 120 and 122 access the common memory part 124 through a QIO library routine 126. A message sent by using the common memory part 124 and QIO library routine 126 is sent without copying data. Therefore, the time of communicating operation between the processes 120 and 122 in a single processor 106 is shortened, and consequently the processing speed of the whole system is increased.

公开(公告)号：JPH1091587A

公开(公告)日：1998-04-10

申请号：JP14526996

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： SONNIER DAVID P ,  BUNTON WILIAM P ,  CUTTS JR RICHARD W ,  KLECKA JAMES S ,  KRAUSE JOHN C ,  WATSON WILLIAM J ,  ZALZALA LINDA E

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To integrate hardware approach in the error check of a processor with software approach. SOLUTION: Routers 14A and 14B are connected to subprocessor systems 10A and 10B as one duplex pair of a multiprocessor system, and I/O packet interfaces 16A and 16B are connected to the routers. A message packet is copied by the routers and sent by a method for surely synchronizing both the paired systems. Since the interruption issued from an I/O element is transmitted by the message packet while containing the information on the factor of interruption similarly to the other information transfer, the interruption can be protected by a CRC and it is not necessary to determine the factor from the side of a CPU. The message packet sent through an I/O has the information of originator or destination and while referring to an external source, for which access to a memory is permitted, from an access suitability verify and transform (AVT) table, a reception CPU verifies whether or not the access is to be permitted.