公开(公告)号：KR101427714B1

公开(公告)日：2014-08-07

申请号：KR1020130135421

申请日：2013-11-08

Applicant: 국민대학교산학협력단

Inventor： 김대환 ,  김동명 ,  전성우

IPC: H01L21/66 ,  H01L29/786

CPC classification number: H01L22/14 ,  H01L22/30 ,  H01L29/78663

Abstract: Disclosed are a method of extracting the surface potential and state density within a band-gap of an amorphous semiconductor thin film transistor using a coupling factor, and a device thereof. The method for extracting the surface potential of the amorphous semiconductor thin film transistor according to an embodiment of the present invention comprises a step of measuring a drain current by a gate voltage of the thin film transistor; a step of extracting a drain current lower than a threshold voltage between the measured drain currents; and a step of extracting the surface potential by the gate voltage of the thin film transistor based on the differentiation of the drain current extracted. The step of extracting the surface potential extracts the surface potential by the gate voltage in the light of a coupling factor included in the surface potential and the extracted drain currents.

Abstract translation: 公开了使用耦合因子提取非晶半导体薄膜晶体管的带隙内的表面电位和状态密度的方法及其装置。 根据本发明实施例的提取非晶半导体薄膜晶体管的表面电位的方法包括通过薄膜晶体管的栅极电压测量漏极电流的步骤; 提取低于测量的漏极电流之间的阈值电压的漏极电流的步骤; 以及基于所提取的漏极电流的微分，通过薄膜晶体管的栅极电压提取表面电位的步骤。 提取表面电位的步骤根据包括在表面电位和提取的漏极电流中的耦合因子，通过栅极电压提取表面电位。

公开(公告)号：KR101378112B1

公开(公告)日：2014-03-26

申请号：KR1020130020316

申请日：2013-02-26

Applicant: 국민대학교산학협력단

Inventor： 배민경 ,  배학열 ,  김대환 ,  김동명

IPC: H01L21/66 ,  H01L29/786

CPC classification number: H01L22/12 ,  H01L29/78693

Abstract: Disclosed is a method for extracting state density in a band gap of an amorphous oxide semiconductor thin film transistor and a device for the same. The method for extracting state density in a band gap of an amorphous oxide semiconductor thin film transistor according to an embodiment of the present invention includes a step of measuring a drain current according to a gate voltage of the thin film transistor; a step of calculating an ideality factor according to the gate voltage by using the measured drain current; a step of differentiating the calculated ideality factor and obtaining a capacitance within a channel based on the differentiated ideality factor; and a step of extracting the state density within the band gap of the thin film transistor based on the obtained capacitance within the cannel. The step of calculating the ideality factor comprises: calculating the ideality factor based on the drain current which is less than or equal to a threshold voltage among the measured drain current so that the state density in the band gap can be extracted without a complex modification. The ideality factor is differentiated so that the accurate state density in the band gap, which is independent to the threshold voltage and is not influenced from heat, light, or temperature, can be extracted. [Reference numerals] (AA) START; (BB) END; (S310) Measuring drain current according to gate voltage; (S320) Calculating an ideal coefficient according to the gate voltage by using the measured drain current; (S330) Differentiating the calculated ideal coefficient; (S340) Obtaining capacitance in a channel based on the differentiated ideal coefficient; (S350) Extracting status density in a band gap based on the capacitance in the obtained channel

Abstract translation: 公开了一种用于提取非晶氧化物半导体薄膜晶体管的带隙中的状态密度的方法及其装置。 根据本发明实施例的用于提取非晶氧化物半导体薄膜晶体管的带隙中的状态密度的方法包括根据薄膜晶体管的栅极电压测量漏极电流的步骤; 通过使用测量的漏极电流来计算根据栅极电压的理想因子的步骤; 基于分解的理想因子，区分计算出的理想因子并获得信道内的电容的步骤; 以及基于所获得的所述容器内的电容提取所述薄膜晶体管的带隙内的状态密度的步骤。 计算理想因子的步骤包括：基于在测量的漏极电流中小于或等于阈值电压的漏极电流来计算理想因子，使得可以在不进行复杂修改的情况下提取带隙中的状态密度。 理想因素是有区别的，因此可以提取与阈值电压无关并且不受热，光或温度影响的带隙中的准确状态密度。 （附图标记）（AA）START; （BB）END; （S310）根据栅极电压测量漏极电流; （S320）使用测定的漏极电流，根据栅极电压计算理想系数; （S330）微分计算的理想系数; （S340）基于差分理想系数获得信道中的电容; （S350）基于获得的通道中的电容提取带隙中的状态密度

公开(公告)号：KR101344754B1

公开(公告)日：2013-12-24

申请号：KR1020130027999

申请日：2013-03-15

Applicant: 국민대학교산학협력단

Inventor： 배학열 ,  최현준 ,  김대환 ,  김동명

IPC: H01L21/66 ,  H01L29/786 ,  G02F1/136

CPC classification number: H01L22/12 ,  H01L22/30 ,  H01L29/78693

Abstract: A method for extracting the density of state within an intrinsic band gap of an amorphous oxide semiconductor thin film transistor and a device thereof are disclosed. The method for extracting the density of state within the intrinsic band gap of the amorphous oxide semiconductor thin film transistor according to the present invention comprises; a step of measuring darkroom capacitance according to gate voltage of a thin film transistor; a step of measuring light reaction capacitance of the thin film transistor by irradiating the thin film transistor with a light source of a predetermined wavelength; a step of applying a first capacitance model and a second capacitance model to an area under flat-band voltage of the thin film transistor and an area over the flat-band voltage of the thin film transistor; and a step of extracting the density of state of an acceptor within the band gap and the density of state of a donor within the band gap based on the darkroom capacitance, the light reaction capacitance, and the applied first and second capacitance models. The present invention extracts the whole density of state within the band gap using experimental measurement data and rapidly simply extracts the whole density of state within the band gap by omitting a repetitive process and a complex calculation. [Reference numerals] (AA) START;(BB) END;(S210) Darkroom capacitance according to gate voltage is measured in a darkroom;(S220) Light reaction capacitance according to gate voltage is measured by irradiating a light source;(S230) Different capacitance model is applied to an area under or over flat voltage (V_FB);(S240) Density of state of a donor within a band gap and the density of state of anacceptor within the band gap are separately extracted based on measured darkroom capacitance, light reaction capacitance, and a capacitance model

Abstract translation: 公开了一种用于提取非晶氧化物半导体薄膜晶体管的固有带隙内的状态密度的方法及其装置。 根据本发明的提取非晶氧化物半导体薄膜晶体管的本征带隙内的状态密度的方法包括： 根据薄膜晶体管的栅极电压测量暗室电容的步骤; 通过用预定波长的光源照射薄膜晶体管来测量薄膜晶体管的光反应电容的步骤; 将第一电容模型和第二电容模型应用于薄膜晶体管的平带电压下的区域和薄膜晶体管的平坦带电压上的面积的步骤; 以及基于暗室电容，光反应电容和所施加的第一和第二电容模型，提取带隙内的受体的状态密度和施加体在带隙内的状态密度的步骤。 本发明使用实验测量数据提取带隙内的整体状态密度，并且通过省略重复处理和复杂计算，快速简单地提取带隙内的整体状态密度。 （参考号）（AA）START;（BB）END;（S210）根据栅极电压的暗室电容在暗室中测量;（S220）通过照射光源测量根据栅极电压的光反应电容;（S230） 不同的电容模型应用于平坦电压（V_FB）以下的区域;（S240）基于测量的暗室电容，单独提取在带隙内的供体的状态密度和带隙内的受体的状态密度， 光反应电容和电容模型

公开(公告)号：KR1020130116651A

公开(公告)日：2013-10-24

申请号：KR1020120039237

申请日：2012-04-16

Applicant: 삼성디스플레이 주식회사 ,  국민대학교산학협력단

Inventor： 임지훈 ,  안병두 ,  김건희 ,  박준현 ,  이제훈 ,  박재우 ,  김대환 ,  정현광 ,  김재형

IPC: H01L29/786 ,  H01L21/336

CPC classification number: G02F1/1368 ,  H01L29/41733 ,  H01L29/7869 ,  H01L27/1225

Abstract: PURPOSE: A thin film transistor, a display device having the same, and a method for manufacturing the same are provided to reduce the negative shift phenomenon of a threshold voltage by preventing a light negative bias thermal stress (LNBTS). CONSTITUTION: A gate electrode (GE) is formed on a base substrate. A first insulating layer is formed on the gate electrode. A semiconductor layer (SM) is formed on the first insulating layer. A source electrode (SE) is formed on the semiconductor layer. A drain electrode (DE) is formed on the first insulating layer.

Abstract translation: 目的：提供薄膜晶体管，具有该薄膜晶体管的显示装置及其制造方法，以通过防止光负偏压热应力（LNBTS）来减小阈值电压的负偏移现象。 构成：在基底基板上形成栅电极（GE）。 在栅电极上形成第一绝缘层。 半导体层（SM）形成在第一绝缘层上。 在半导体层上形成源电极（SE）。 漏电极（DE）形成在第一绝缘层上。

公开(公告)号：KR1020130046317A

公开(公告)日：2013-05-07

申请号：KR1020110110835

申请日：2011-10-27

Applicant: 국민대학교산학협력단

Inventor： 김대환 ,  김동명 ,  김재형 ,  정현광

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78696 ,  H01L29/06 ,  H01L29/78663

Abstract: PURPOSE: An amorphous semiconductor thin film transistor with an active layer doped with different concentrations and a manufacturing method thereof are provided to improve stability by making the doping concentration of a semiconductor layer different. CONSTITUTION: A gate is formed on a substrate. A gate insulating layer is formed on the gate. Semiconductor layers doped with different concentrations are laminated to form an active layer(140). A source(150) is in contact with the active layer. A drain(160) is in contact with the active layer.

Abstract translation: 目的：提供具有掺杂不同浓度的有源层的非晶半导体薄膜晶体管及其制造方法，以通过使半导体层的掺杂浓度不同而提高稳定性。 构成：在基板上形成栅极。 在栅极上形成栅极绝缘层。 掺杂不同浓度的半导体层被层压以形成有源层（140）。 源（150）与有源层接触。 漏极（160）与有源层接触。

公开(公告)号：KR101102671B1

公开(公告)日：2012-01-05

申请号：KR1020100045681

申请日：2010-05-14

Applicant: 국민대학교산학협력단

Inventor： 김동명 ,  김대환 ,  이순영 ,  장재만 ,  김효종 ,  신자선

IPC: H01L27/108 ,  H01L21/8242

Abstract: 본 발명은 커패시터가 없는 SBE 디램 셀 트랜지스터에 관한 것으로서, 보다 구체적으로는 충돌 이온화(Impact Ionization)에 의해 생성되는 홀이 빠져나가는 것을 물리적으로 방해하기 위하여 형성된 이산화실리콘(SiO
2 ) 장벽; 이산화실리콘 장벽의 상단에 형성되는 한 쌍의 실리콘(Si) 소스/드레인 층; 상기 이산화실리콘(SiO
2 ) 장벽에 둘러싸이며, 상기 한 쌍의 실리콘 소스/드레인 층 사이에 인접하여 형성되는, 결정구조의 실리콘(Si) 채널 층; 및 상기 실리콘 채널 층 하단에 이종 접합되며 충돌 이온화에 의해 생성되는 홀을 저장하는 실리콘저마늄(SiGe)층을 포함하는 것을 그 구성상의 특징으로 한다.
본 발명에서 제안하고 있는 커패시터가 없는 SBE 디램 셀 트랜지스터에 따르면, 실리콘 채널 아래에 있는 실리콘저마늄 층이, 실리콘 층과 실리콘저마늄 층 사이의 밴드 오프셋을 이용하여 홀을 가둠으로써 전하 유지 특성을 향상시킬 수 있다.
또한, 반복된 실리콘/실리콘저마늄 구조를 통하여 격자의 불일치로 인한 결함을 줄일 수 있으며, 이산화실리콘으로 만들어진 물리적인 장벽이 홀의 저장 공간과 소스/드레인을 분리시켜 데이터 '1'의 쓰기 동작 동안 생성된 홀들이 빠져 버리는 것과 홀을 저장하는 실리콘저마늄층에서의 SRH 재결합이 발생하는 것 모두를 차단할 수 있다.
뿐만 아니라, 상부 게이트 워드 라인과 하부 게이트 워드 라인을 다른 금속 층으로 구성하고, 셀 배열에서 소스를 한 개의 비트 라인으로 공유하여 결과적으로 셀의 최소 배선 폭을 줄여 4F
2 의 셀 크기를 얻을 수 있다.

公开(公告)号：KR1020110139485A

公开(公告)日：2011-12-29

申请号：KR1020100059606

申请日：2010-06-23

Applicant: 국민대학교산학협력단

Inventor： 김대환 ,  정인영

IPC: G01N33/48 ,  G01N27/02 ,  G01N21/00 ,  G01N7/00

Abstract: PURPOSE: A biochip and a biochemical analysis system using the same are provided to accurately measure the concentration of a target molecule. CONSTITUTION: A biochip(100) comprises: a biosensor(101) in which electric conductivity is changed according to the interaction between target units; an environmental variable sensor(160) which is integrated with the biosensor and provides output value changing according to the environmental variable; and a substrate on which the biosensor and the environmental variable sensor are arranged.

Abstract translation: 目的：提供一种生物芯片和使用该生物芯片的生化分析系统，以准确测量靶分子的浓度。 构成：生物芯片（100）包括：生物传感器（101），其中根据目标单元之间的相互作用改变导电性; 环境变量传感器（160），其与所述生物传感器集成，并且根据所述环境变量提供输出值变化; 和布置有生物传感器和环境变量传感器的基板。

公开(公告)号：KR100942240B1

公开(公告)日：2010-02-16

申请号：KR1020090064183

申请日：2009-07-14

Applicant: 국민대학교산학협력단

Inventor： 김동명 ,  김대환 ,  이순영

IPC: H01L27/115 ,  G11C16/04

CPC classification number: H01L29/7855 ,  H01L21/28282 ,  G11C16/04 ,  H01L21/265 ,  H01L21/31051

Abstract: PURPOSE: A multi-bit-per cell non-volatile memory cell and a method of operating for the multi-bits cell operation are provided to perform in rapidly at a lower voltage while a recording and erasing operation by using reading a gate induced drain leakage. CONSTITUTION: An active pin for a source and a drain region is patterned at the both sides of a silicon substrate by using a hard mask pattern with a mask. An oxide film is deposited after removing the hard mask pattern. The first oxide film is formed at the active area for resource and drain region. A poly-silicon is deposited. T-shape gate is patterned by using a deposited poly-silicon with the hard mask. A second oxide film is formed on a gate region of T-shape.

Abstract translation: 目的：提供一个多位单元非易失性存储单元和一种操作多位单元操作的方法，以在较低电压下快速执行，同时通过读取栅极感应漏极泄漏进行记录和擦除操作 。 构成：通过使用具有掩模的硬掩模图案，在硅衬底的两侧上对源极和漏极区域的有源引脚进行构图。 去除硬掩模图案后，沉积氧化膜。 第一氧化物膜形成在用于资源和漏极区域的有源区域。 沉积多晶硅。 通过使用具有硬掩模的沉积的多晶硅来对T形栅极进行图案化。 在T形的栅极区域上形成第二氧化膜。

公开(公告)号：KR1020150081709A

公开(公告)日：2015-07-15

申请号：KR1020140001460

申请日：2014-01-06

Applicant: 국민대학교산학협력단

Inventor： 김대환 ,  김동명 ,  이지은

IPC: G01N27/416 ,  G01N27/327 ,  G01N27/414

CPC classification number: G01N27/416 ,  G01N27/327 ,  G01N27/414

Abstract: 본발명은디지털화신호처리부가집적된바이오센서및 감지방법에관한것으로, 보다상세하게는하향식(top-down approach) 제조공정을이용하여디지털화(Digitizer) 신호처리부와상호보완적인(Complementary) 바이오센서가집적된바이오센서및 바이오물질감지방법에관한것이다. 본발명에서는반도체특성을가지는나노소자의게이트전압에대한바이오물질과수용체(receptor)의반응에따른감지신호를생성하여상태변수에따라디지털화된비트(digitized bit)의테이블을측정하고, 측정된디지털레벨각각을저장하여바이오물질의감지속도를높이고, 민감도를높이는것을목적으로한다.

Abstract translation: 本发明涉及一种与数字化信号处理部分和感测方法相结合的生物传感器，更具体地说，涉及一种利用自上而下的方法处理将互补生物传感器与数字化信号处理部件集成的生物传感器， 和生物材料感测方法。 本发明能够根据状态变量通过根据受体和生物材料与具有半导体特性的纳米元件的栅极电压的反应产生感测信号来测量数字化位的表格，并且增加 通过存储每个测量的数字电平，生物材料的灵敏度和感测速度。

公开(公告)号：KR101529704B1

公开(公告)日：2015-06-18

申请号：KR1020140009660

申请日：2014-01-27

Applicant: 국민대학교산학협력단

Inventor： 김대환 ,  김동명 ,  이경민

IPC: H01L21/66 ,  H01L29/786

CPC classification number: H01L22/14 ,  H01L22/30 ,  H01L29/78663

Abstract: 비정질반도체박막트랜지스터의이동도추출방법및 그장치가개시된다. 본발명의일 실시예에따른비정질반도체박막트랜지스터의이동도추출방법은상기박막트랜지스터의밴드갭내 상태밀도를획득하는단계; 상기추출된상기밴드갭내 상태밀도를이용하여문턱전압보다낮은전압영역에대한상기박막트랜지스터의제1 이동도를계산하는단계; 상기박막트랜지스터의측정된게이트전압에따른측정데이터와상기게이트전압에따른측정데이터의미리정의된수학적모델을비교하여상기문턱전압보다높은전압영역에대한상기박막트랜지스터의제2 이동도를계산하는단계; 및상기계산된상기제1 이동도와상기제2 이동도를이용하여상기박막트랜지스터의이동도를추출하는단계를포함한다.

Abstract translation: 公开了提取非晶半导体薄膜晶体管的迁移率的方法和装置。 根据本发明的实施例的提取非晶半导体薄膜晶体管的迁移率的装置包括获得薄膜晶体管的带隙中的状态密度的步骤; 通过使用所提取的状态密度来计算比阈值电压低的电压区域的薄膜晶体管的第一迁移率的步骤; 通过根据栅极电压和测量数据根据薄膜晶体管的测量栅极电压比较测量数据的预定数学模型，计算比阈值电压高的电压区域的薄膜晶体管的第二迁移率的步骤 ; 以及通过使用所计算的第一和第二迁移率来提取薄膜晶体管的迁移率的步骤。