公开(公告)号：KR100375986B1

公开(公告)日：2003-03-15

申请号：KR1020000070879

申请日：2000-11-27

Applicant: 삼성전자주식회사

Inventor： 김남석 ,  조욱래

IPC: G11C11/00

CPC classification number: H03H21/0001 ,  H03H11/405

Abstract: Disclosed is a programmable impedance control circuit, comprising a voltage divider, the voltage divider comprising an MOS array supplied with a first voltage and an external resistance having an external impedance equal to N times said external resistance. The voltage divider outputs a second voltage. A reference voltage generator is provided for generating a third voltage corresponding to N/(N+M) times said first voltage as a reference voltage for said second voltage, and wherein M times internal impedance is used for N times external impedance (N=M or N<>M).

Abstract translation: 公开了一种可编程阻抗控制电路，其包括分压器，所述分压器包括被提供有第一电压的MOS阵列和具有等于所述外部电阻的N倍的外部阻抗的外部电阻。 分压器输出第二个电压。 提供参考电压发生器，用于产生对应于作为所述第二电压的参考电压的所述第一电压的N /（N + M）倍的第三电压，并且其中M倍内部阻抗用于N倍外部阻抗（N = M 或N≠M）。

公开(公告)号：KR1020010055009A

公开(公告)日：2001-07-02

申请号：KR1019990056061

申请日：1999-12-09

Applicant: 삼성전자주식회사

Inventor： 한장원 ,  김민일 ,  김남석 ,  홍인표

IPC: H01L23/495

CPC classification number: H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PURPOSE: A lead frame having a pre-plated part is provided to prevent degradation of bonding strength between the lead frame and molding resin and thereby to improve reliability of a package using the lead frame. CONSTITUTION: The lead frame(200) includes a plurality of leads(130), which are arranged in a pair of rows. Each of the leads(130) has an inner lead(110) to be connected with a bonding pad of a semiconductor chip, and an outer lead(120) extended from the inner lead(110) and also fastened to a side rail(140). The lead frame(200) further has a plating layer(132) previously formed on the leads(130) before forming the package to enhance the bonding strength between the leads(130) and the molding resin. In particular, the lead frame(200) has the pre-plated part(D) where the plating layer(132) is formed, and a non-plated part(C) where the plating layer(132) is not formed. When the inner and outer leads(110,120) are distinguished from each other by a boundary line(A), the pre-plated part(D) and the non-plated part(C) are separated by an imaginary dividing line(B) which is located inward from the boundary line(A).

Abstract translation: 目的：提供具有预镀部分的引线框架，以防止引线框架和模制树脂之间的结合强度降低，从而提高使用引线框架的封装的可靠性。 构成：引线框架（200）包括以一对排布置的多个引线（130）。 每个引线（130）具有与半导体芯片的接合焊盘连接的内部引线（110）和从内部引线（110）延伸的外部引线（120），并且还固定到侧部导轨（140） ）。 引线框架（200）还具有在形成封装之前预先形成在引线（130）上的镀层（132），以增强引线（130）和模制树脂之间的结合强度。 特别地，引线框架（200）具有形成有镀层（132）的预镀部（D）和不形成镀层（132）的非电镀部（C）。 当通过边界线（A）将内引线和外引线（110,120）彼此区分开时，预镀部分（D）和非电镀部分（C）由假想分界线（B）分开， 位于边界线（A）的内侧。

公开(公告)号：KR1020010046385A

公开(公告)日：2001-06-15

申请号：KR1019990050138

申请日：1999-11-12

Applicant: 삼성전자주식회사

Inventor： 김남석 ,  홍인표

IPC: H01L23/28

Abstract: PURPOSE: A dual chip package and a manufacturing method thereof are provided to attain a high memory density in a package level. CONSTITUTION: The dual chip package(100) includes two semiconductor chips(10,20) attached on both faces(31,33) of a printed circuit board(30) and electrically connected to circuit patterns(35,37) formed on the respective faces(31,33) through metal wires(41,43). In the package(100), the corresponding circuit patterns(35,37) are electrically connected to each other through a via hole(39), and the respective upper circuit patterns(35) are bonded to vertically extended metal wires(45). Furthermore, one end of each vertically extended metal wire(45) is coupled to a ball pad(50) formed on a top surface(72) of a package body(70), and also a solder ball(60) is mounted on the corresponding ball pad(50). In addition, the vertically extended metal wires(45) are preferably plated with nickel to enhance strength thereof.

Abstract translation: 目的：提供双芯片封装及其制造方法以在封装级别中获得高存储密度。 构成：双芯片封装（100）包括安装在印刷电路板（30）的两个面（31,33）上的两个半导体芯片（10,20），并且电连接到形成在各自的电路图案（35,37）上 （31,33）穿过金属线（41,43）。 在封装（100）中，相应的电路图案（35,37）通过通孔（39）彼此电连接，并且各个上电路图案（35）被接合到垂直延伸的金属线（45）。 此外，每个垂直延伸的金属线（45）的一端连接到形成在封装体（70）的顶表面（72）上的球垫（50），并且焊球（60）安装在 相应的球垫（50）。 此外，垂直延伸的金属线（45）优选地镀有镍以增强其强度。

公开(公告)号：KR1020010044863A

公开(公告)日：2001-06-05

申请号：KR1019990047902

申请日：1999-11-01

Applicant: 삼성전자주식회사

Inventor： 김민일 ,  김남석

IPC: H01L21/60

CPC classification number: H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A wireless lead-on-chip(LOC) package is provided to simplify a manufacturing process by omitting a wire bonding process, and to decrease the LOC package in thickness by reducing the entire height of the package by the height of a wire loop formed by a bonding wire. CONSTITUTION: A semiconductor chip(110) has an active surface(114) in which are a plurality of center pads(112). A plurality of leads(120) includes a plurality of inner leads(122) adhered to the upper portion of the active surface. Molding resin(150) encapsulates a region including the semiconductor chip and the inner leads. An end(124) of the inner leads is down-set to be directly bonded to the corresponding center pads.

Abstract translation: 目的：提供无线片上（LOC）封装，以通过省略引线接合工艺来简化制造过程，并通过将封装的整个高度降低线圈的高度来减小LOC封装的厚度 由接合线形成。 构成：半导体芯片（110）具有多个中心焊盘（112）的有源表面（114）。 多个引线（120）包括粘附到有源表面的上部的多个内引线（122）。 成型树脂（150）封装包括半导体芯片和内部引线的区域。 内引线的端部（124）被下降以直接接合到相应的中心焊盘。

公开(公告)号：KR1020000015326A

公开(公告)日：2000-03-15

申请号：KR1019980035175

申请日：1998-08-28

Applicant: 삼성전자주식회사

Inventor： 장동현 ,  김남석 ,  강사윤 ,  권흥규

IPC: H01L21/60

CPC classification number: H01L24/94 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/11 ,  H01L24/12 ,  H01L29/0657 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/013

Abstract: PURPOSE: A method for manufacturing a chip scale package in a wafer state is provided, which forms a metal wire and an insulating layer on a semiconductor wafer to manufacture a chip scale package. CONSTITUTION: The method for manufacturing a chip scale package in a wafer state comprises the steps of: providing a semiconductor wafer (10) having a chip cutting region between integrated circuit chips; forming a metal wire layer (66) to be electrically connected to chip pads (12); covering an insulating layer (68) having a certain thickness on an inactive layer (14) and the metal wire layer (66) and removing a part of the insulating layer (68) to form a ball pad (70); forming a solder ball (74) to the ball pad (70); and cutting the semiconductor wafer (10) to divide each integrated circuit for obtaining a chip scale package. Thereby, it is possible to decrease the manufacturing cost.

Abstract translation: 目的：提供一种用于制造晶片状态的芯片级封装的方法，其在半导体晶片上形成金属线和绝缘层，以制造芯片级封装。 构成：制造晶片状态的芯片级封装的方法包括以下步骤：提供在集成电路芯片之间具有切屑区域的半导体晶片（10）; 形成电连接到芯片焊盘（12）的金属线层（66）; 在非活性层（14）和所述金属丝层（66）上覆盖具有一定厚度的绝缘层（68），并且去除所述绝缘层（68）的一部分以形成球垫（70）; 向所述球垫（70）形成焊球（74）; 以及切割半导体晶片（10）以划分每个集成电路以获得芯片级封装。 由此，能够降低制造成本。

公开(公告)号：KR1019990069950A

公开(公告)日：1999-09-06

申请号：KR1019980004538

申请日：1998-02-16

Applicant: 삼성전자주식회사

Inventor： 김남석 ,  이권우 ,  최완균

IPC: H01L23/48

Abstract: 본 발명에 의한 플립칩본딩구조 및 이에 적용된 솔더범프의 제조방법은 반도체기판의 본딩패드와 기판의 접속패턴의 적어도 일측에 무전해도금 니켈층이 사다리꼴 형태로 소정 높이만큼 형성되어 있고, 상기 니켈층의 표면에 금 재질의 산화방지층이 무전해도금법에 의해 형성되어 있고, 상기 산화방지층의 표면에 솔더층이 스크린프린팅법, 전기도금법 또는 무전해도금법에 의해 형성되어 있다.
따라서, 본 발명은 고 종횡비의 니켈층을 본딩패드에 형성할 수 있으므로 본딩패드의 미세피치를 희생하지 않으며 상기 반도체칩과 기판을 플립칩본딩할 수 있고 또한 상기 니켈층을 지지층으로 작용시켜 솔더접합의 전단 스트레스를 증가시킬 수 있을 뿐만 아니라 피로수명을 연장시킬 수 있어 플립칩본딩의 신뢰성을 향상시킬 수 있다.

公开(公告)号：KR2019900001050U

公开(公告)日：1990-01-18

申请号：KR2019880008621

申请日：1988-06-02

Applicant: 삼성전자주식회사

Inventor： 김효덕 ,  김남석

IPC: F24F1/02 ,  F24F13/28

公开(公告)号：KR101501739B1

公开(公告)日：2015-03-11

申请号：KR1020080026413

申请日：2008-03-21

Applicant: 삼성전자주식회사

Inventor： 이택훈 ,  김평완 ,  김남석 ,  장철용

IPC: H01L23/12

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/82

Abstract: 반도체 패키지와 모듈 및 그 제조 방법들이 설명된다. 본 발명의 일 실시예에 의한 반도체 패키지는, 뒷면이 서로 접착되고 앞면으로 노출된 칩 패드들을 갖는 두 개의 반도체 칩들, 접착된 두 반도체 칩들의 측면들을 감싸며 형성된 봉지부, 봉지부를 관통하며 형성된 비아 플러그들, 두 반도체 칩들의 노출된 표면들 및 봉지부들의 표면들 상에 형성되며 칩 패드들 및 비아 플러그들의 표면을 노출시키는 절연층, 및 노출된 칩 패드들의 표면 및 비아 플러그들의 표면 상에 형성된 패키지 패드들을 포함한다.
반도체 패키지, 반도체 모듈, 재배선 구조

公开(公告)号：KR1020100012329A

公开(公告)日：2010-02-08

申请号：KR1020080073666

申请日：2008-07-28

Applicant: 삼성전자주식회사

Inventor： 유혜정 ,  안은철 ,  정태경 ,  김남석

IPC: H01L23/12

CPC classification number: H01L21/565 ,  H01L23/5387 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/24226 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2224/82

Abstract: PURPOSE: A method of forming an electric device having stacked chips is provided to improve the productivity of the electronic device by performing one process for rewiring. CONSTITUTION: The chips are formed to be separated on the substrate(1). The rewiring(20) is electrically interlinked with the chips. Before the rewiring is formed, the molding film is formed between the chips. The grooves are formed between the chips.

Abstract translation: 目的：提供一种形成具有堆叠芯片的电子装置的方法，以通过执行一个重新布线处理来提高电子装置的生产率。 构成：将芯片形成为在衬底（1）上分离。 重新布线（20）与芯片电连接。 在重新布线形成之前，在芯片之间形成成型膜。 凹槽形成在芯片之间。

公开(公告)号：KR1020090123280A

公开(公告)日：2009-12-02

申请号：KR1020080049271

申请日：2008-05-27

Applicant: 삼성전자주식회사

Inventor： 이택훈 ,  김평완 ,  김남석

IPC: H01L21/301 ,  H01L21/268

CPC classification number: H01L21/78 ,  B23K26/364 ,  B23K26/40 ,  B23K2203/172 ,  B23K2203/50 ,  B28D5/00 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: PURPOSE: A manufacturing method of a semiconductor chip package, a semiconductor wafer, and a cutting method thereof are provided to prevent damage to a wafer due to a laser used in cutting an encapsulation layer by successively irradiating at least two kinds of lasers to a scribe lane. CONSTITUTION: A protection layer(150) is formed on a scribe lane(103) of a wafer(100) in which a plurality of semiconductor chips(101,102) is formed. An encapsulation layer(190) is formed on a top part of the protection layer and the semiconductor chips. The semiconductor chips are divided by successively irradiating at least two kinds of lasers to the scribe lane in which the protection layer is formed. The encapsulation layer formed on the top part of the protection layer is cut by irradiating a first laser to the scribe lane. The protection layer and the wafer are cut by irradiating a second laser having a wavelength lower than the first laser to the scribe lane.

Abstract translation: 目的：提供半导体芯片封装，半导体晶片及其切割方法的制造方法，以通过将至少两种激光依次照射到划线器来防止由于用于切割封装层而使用的激光而对晶片的损坏 车道。 构成：在其上形成有多个半导体芯片（101,102）的晶片（100）的划线（103）上形成保护层（150）。 在保护层的顶部和半导体芯片上形成封装层（190）。 半导体芯片通过将至少两种激光依次照射到其中形成保护层的划线。 通过将第一激光照射到划线，切割形成在保护层顶部的封装层。 通过将具有低于第一激光的波长的第二激光器照射到划线来切割保护层和晶片。