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公开(公告)号：KR1020130045696A
公开(公告)日：2013-05-06
申请号：KR1020110110073
申请日：2011-10-26
Applicant: 삼성전자주식회사
IPC: H01L21/58
CPC classification number: H01L21/6836 , H01L2221/68336
Abstract: PURPOSE: An apparatus for fabricating a semiconductor package and a fabricating method using the same are provided to separate a die attach film at regular intervals and to prevent divided die attach films from being combined with each other. CONSTITUTION: An apparatus for fabricating a semiconductor package includes a wafer ring(30), a wafer ring holder, a first plunger(200), and a second plunger(300). The wafer ring includes a hollow and fixes a substrate. The wafer ring holder fixes the wafer ring. The substrate is adhered on a tape and positioned in the hollow. The tape is adhered to the wafer ring. The first plunger and the second plunger are separated from each other and moves between the substrate and the wafer ring in the hollow in a first direction.
Abstract translation: 目的：提供一种用于制造半导体封装的装置及其制造方法，以便以规则的间隔分开芯片附着膜并防止分开的芯片附着膜彼此组合。 构成：用于制造半导体封装的装置包括晶片环（30），晶片环保持器，第一柱塞（200）和第二柱塞（300）。 晶圆环包括中空并固定基板。 晶圆环座固定晶圆环。 将基板粘附在带上并定位在中空部分中。 胶带粘附到晶圆环上。 第一柱塞和第二柱塞彼此分离，并且在第一方向上在空腔中在基板和晶片环之间移动。
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公开(公告)号：KR1020100012329A
公开(公告)日：2010-02-08
申请号：KR1020080073666
申请日：2008-07-28
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L21/565 , H01L23/5387 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/24226 , H01L2224/76155 , H01L2224/82102 , H01L2224/97 , H01L2225/06524 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2225/1064 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/15311 , H01L2224/82
Abstract: PURPOSE: A method of forming an electric device having stacked chips is provided to improve the productivity of the electronic device by performing one process for rewiring. CONSTITUTION: The chips are formed to be separated on the substrate(1). The rewiring(20) is electrically interlinked with the chips. Before the rewiring is formed, the molding film is formed between the chips. The grooves are formed between the chips.
Abstract translation: 目的：提供一种形成具有堆叠芯片的电子装置的方法，以通过执行一个重新布线处理来提高电子装置的生产率。 构成：将芯片形成为在衬底（1）上分离。 重新布线（20）与芯片电连接。 在重新布线形成之前，在芯片之间形成成型膜。 凹槽形成在芯片之间。
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公开(公告)号：KR1020090117097A
公开(公告)日：2009-11-12
申请号：KR1020080042997
申请日：2008-05-08
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/2889 , G01R1/06716 , G01R1/06733
Abstract: PURPOSE: A probe card with a rewiring probe structure and a probe card module using the same are provided to test a silicon wafer according to the temperature history. CONSTITUTION: A probe card(40) with a rewiring probe structure includes a wafer(24,30) for the probe card, a penetration via electrode, and a rewiring probe structure. A plurality of penetration via electrodes(26a,32) pass through the wafer for the probe card. A rewiring probe structure(26b) of the twisted cage type is connected to the penetration via electrodes and is protruded from the one side of the wafer for the probe card.
Abstract translation: 目的：提供具有重新布线探针结构的探针卡和使用其的探针卡模块，以根据温度历史测试硅晶片。 构成：具有重新布线探针结构的探针卡（40）包括用于探针卡的晶片（24,30），穿透通孔电极和重新布线探针结构。 多个穿透通孔电极（26a，32）穿过用于探针卡的晶片。 扭转笼型的重新布线探针结构（26b）连接到穿透通孔电极，并从用于探针卡的晶片的一侧突出。
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公开(公告)号：KR1020060029925A
公开(公告)日：2006-04-07
申请号：KR1020040078790
申请日：2004-10-04
Applicant: 삼성전자주식회사
CPC classification number: H01L25/50 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/1134 , H01L2224/1308 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/78301 , H01L2224/83136 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
Abstract: A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having overhang portions, and at least one bump interposed between the substrate and the overhang portions. The at least one bump may support the overhang portions and may be formed when the first electrical connection is formed.
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公开(公告)号：KR100403619B1
公开(公告)日：2003-10-30
申请号：KR1020010008758
申请日：2001-02-21
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/05 , H01L23/3114 , H01L24/03 , H01L24/45 , H01L24/48 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/45144 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2924/00
Abstract: 빔 리드 본딩시 가해지는 열적/기계적 스트레스에 기인하여 본드패드 메탈층 하부의 절연막이 손상을 받는 문제를 억제할 수 있는 반도체 소자의 본드패드 및 그 형성방법에 관해 개시한다. 이를 위해 본 발명은 제1 메탈층과 제2 메탈층이 직접 접착된 형태의 본드패드 메탈층과 그 하부에 위치하는 절연막 사이에 플레이트 폴리실리콘층을 추가로 형성하여, 외부로부터 가해지는 열적/기계적 스트레스(thermo-Mechanical stress)를 흡수케하고, 수직방향의 인장력에 대한 내구성을 증대시키며, 본드패드 메탈층과 절연막의 미끄러짐을 방지하고 접착성을 개선할 수 있는 반도체 소자의 본드패드 및 그 형성방법을 제공한다.
Abstract translation: 根据本发明的各种实施例，半导体器件的焊盘结构减少了光束引线接合中由热机械应力引起的损伤。 还提供了一种制造改进的焊盘结构的方法。 优选在接合焊盘金属层和电介质层之间形成多晶硅膜片。 多晶硅薄膜板吸收外部热机械应力，并提高粘合拉伸试验（BPT）中的焊盘的耐久性。 接合焊盘金属层和电介质层之间的接合也得到改善。 还提供了其他特点和优点。
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Patent Agency Ranking
公开(公告)号：KR1020030048250A
公开(公告)日：2003-06-19
申请号：KR1020010078137
申请日：2001-12-11
Applicant: 삼성전자주식회사
IPC: H01L23/10
CPC classification number: H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
Abstract: PURPOSE: A multi-chip package is provided to be capable of overcoming the unstability of a bonding wire and the problem of routing by using a dummy chip including a circuit pattern. CONSTITUTION: A plurality of board pads(138) and solder pads are formed on the upper and lower portion of a board(130), respectively. A plurality of chips(111,121,131,141) are stacked on the board using an adhesive, wherein chips have chip pads(117,127,137,147), respectively. A dummy chip(210) having a metal pattern is stacked in the middle of the chips. A plurality of bonding wires(112,122,132,133,142,143) are used for connecting between chips and dummy chip, dummy chip and board, and chips and board. A plurality of solder balls(140) are attached on the lower portion of the board through solder pads. The upper portion of the resultant structure is enclosed with a molding part(160).
Abstract translation: 目的：提供一种能够克服接合线的不稳定性的多芯片封装以及通过使用包括电路图案的虚设芯片进行布线的问题。 构成：在板（130）的上部和下部分别形成多个板焊盘（138）和焊盘。 使用粘合剂将多个芯片（111,121,131,141）堆叠在板上，其中芯片分别具有芯片焊盘（117,127,137,147）。 具有金属图案的虚设芯片（210）堆叠在芯片的中间。 多个接合线（112,122,132,133,142,143）用于芯片和虚拟芯片，虚拟芯片和板，芯片和板之间的连接。 通过焊盘将多个焊球（140）附接在板的下部。 所得结构的上部由模制部件（160）封闭。
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公开(公告)号：KR1020010068506A
公开(公告)日：2001-07-23
申请号：KR1020000000455
申请日：2000-01-06
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/91 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/49 , H01L2224/4918 , H01L2224/73215 , H01L2224/73265 , H01L2924/01082 , H01L2924/1532 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: PURPOSE: A semiconductor package with a double density integration circuit is provided to minimize a height of a package without laminating semiconductor chips. CONSTITUTION: The first connection portion(132) such as a bonding pad is formed on the first active face(130). The second connection portion(142) such as a bonding pad is formed on the second active face(140). An adhesive(170) such as a tape for LOC(Lead On Chip) is located on the first and the second active faces(130,140). Inner leads(112) are attached by the adhesive(170). The bonding pads(132,142) are connected electrically with the inner leads(112) by a bonding pad(160). A region including the bonding pads(132,142) and the inner leads(112) is molded by a molding member such as a molding resin(150).
Abstract translation: 目的：提供具有双密度积分电路的半导体封装，以最小化封装的高度而不层压半导体芯片。 构成：诸如焊盘的第一连接部分（132）形成在第一主动面（130）上。 诸如焊盘的第二连接部分（142）形成在第二主动面（140）上。 诸如用于LOC（片上芯片）的带的粘合剂（170）位于第一和第二有效面（130,140）上。 内引线（112）通过粘合剂（170）附着。 接合焊盘（132,142）通过接合焊盘（160）与内部引线（112）电连接。 包括接合焊盘（132,142）和内部引线（112）的区域由诸如模制树脂（150）的模制构件模制。
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公开(公告)号：KR1020000020354A
公开(公告)日：2000-04-15
申请号：KR1019980038949
申请日：1998-09-21
Applicant: 삼성전자주식회사
IPC: H01L23/02
Abstract: PURPOSE: A KGD(known good die) is provided to use a prior test socket and to reduce the fabrication cost of the KGD. CONSTITUTION: A KGD carrier connects a semiconductor chip(110) to a test socket electrically in order to be applied in carrying an individual semiconductor chip or in electrical function test and burn-in test. BGA(Ball Grid Array) solder balls(150) are formed on the bottom surface of a film(130) where the semiconductor chip is mounted or a structure of the KGD carrier including a clip lead contacting the top/bottom surface of the substrate. Through the above structure, an additional cost is prevented and further the fabrication cost of the KGD is reduced by applying the KGD in the prior test socket.
Abstract translation: 目的：提供KGD（已知良好的模具）以使用先前的测试插座，并降低KGD的制造成本。 构成：KGD载体将半导体芯片（110）电连接到测试插座，以便用于承载单个半导体芯片或电气功能测试和老化测试。 在安装有半导体芯片的膜（130）的底面上形成有BGA（球栅阵列）焊球（150），或者包括与基板的顶面/底面接触的夹头的KGD载体的结构。 通过上述结构，可以防止额外的成本，并且通过将KGD应用在先前的测试插座中来进一步降低KGD的制造成本。
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公开(公告)号：KR1019970030547A
公开(公告)日：1997-06-26
申请号：KR1019950043179
申请日：1995-11-23
Applicant: 삼성전자주식회사
IPC: H01L21/603
Abstract: 본 발명은 열압착 수단을 이용한 이종의 전자 재료 접합 방법에 있어서, 소정의 온도로 열압착 수단을 가온하는 가온단계와, 이종의 전자 재료를 열압착 수단으로 가압하여 접합하는 가압단계와, 이종 전자 재료의 온도를 측정하는 온도측정 단계와, 기준 온도와의 차이값을 열압착 수단에 보상하는 보상단계로 이루어진 것을 특징으로 하는 열압착 수단을 이용한 이종 전자 재료의 접합 방법을 제공함으로써, 접합 계면 온도를 실제 접합하는 순간 접합 계합의 온도를 측정하여 재료의 표면 거칠기, 도금상태 등의 표면상태가 달라도 접합 계면 온도를 일정하게 조절하여 접합 강도의 오차를 극단적으로 줄여 이종 전자 재료 접합의 신뢰성을 개선하는 효과를 나타낸다.
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公开(公告)号：KR1019960019687A
公开(公告)日：1996-06-17
申请号：KR1019940030245
申请日：1994-11-17
Applicant: 삼성전자주식회사
IPC: H01L23/495
Abstract: 반도체 칩을 탑재하기 위한 다이 패드 및 프린트 회로 기판 및 테스트 기판에 전기적으로 접속할 수 있는 리드를 구비하는 반도체용 리드프레임에 있어서 상기 리드프레임은, 상기 다이 패드의 일표면에 형성된 홈; 및 상기 홈에 형성되고 전기적으로 도금된 클래드(electro plating clad)층을 구비하는 것을 특징으로 하는 반도체용 리드프레임을 제공한다.
본 발명에 따르면, 전기적 도금에 의해 이종소재 접합 리드프레임을 제조함으로써, 종래 리드프레임 형상에 따른 제약을 극복할 수 있으며, 불필요한 부분에 클래드층을 형성하는 것을 방지하여, 에칭 리드프레임 제조시의 치수 불안정을 해결할 수 있다.
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