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公开(公告)号：KR1020090025631A
公开(公告)日：2009-03-11
申请号：KR1020070090618
申请日：2007-09-06
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5642 , G11C16/3418
Abstract: A memory system having memory cells capable of storing multi bit data and a reading method thereof are provided to secure a reading margin by correcting data according to a program state of a memory cell. A non volatile memory device(1100) has memory cells for storing multi bit data. A memory controller(1200) controls the non volatile memory device. The memory controller is based on data read from memory cells adjacent to a selected memory cell in a reading operation, and determines whether or not a state of the data read from the selected memory cell is changed into a different state when peripheral memory cells are programmed. The memory controller corrects the data read from the selected memory cell according to a determined result.
Abstract translation: 提供具有能够存储多位数据的存储单元及其读取方法的存储器系统，以通过根据存储器单元的程序状态校正数据来确保读取余量。 非易失性存储器件（1100）具有用于存储多位数据的存储器单元。 存储器控制器（1200）控制非易失性存储器件。 存储器控制器基于在读取操作中从与所选择的存储器单元相邻的存储单元读取的数据，并且当外围存储器单元被编程时，确定从所选存储单元读取的数据的状态是否变为不同状态 。 存储器控制器根据确定的结果校正从所选择的存储器单元读取的数据。
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公开(公告)号：KR1020090017270A
公开(公告)日：2009-02-18
申请号：KR1020070081886
申请日：2007-08-14
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C16/0483 , G11C2211/5641
Abstract: A multi-bit programming device and a method thereof are provided to improve a confidence level of data and to increase the number of bits stored in total memory cells. A multi-bit programming device(100) includes a first programming unit and a second programming unit. The first programming unit stores data of a first bit number in one or more first memory cells(113) connected to one or more first bit lines(111). The second programming unit stores data of a second bit number in one or more second memory cells(114) connected to one or more second bit lines(112).
Abstract translation: 提供了一种多位编程设备及其方法，以提高数据的置信度并增加存储在总存储单元中的位数。 多位编程设备（100）包括第一编程单元和第二编程单元。 第一编程单元将连接到一个或多个第一位线（111）的一个或多个第一存储单元（113）中的第一位数的数据存储。 第二编程单元将连接到一个或多个第二位线（112）的一个或多个第二存储单元（114）中的第二位数的数据存储。
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公开(公告)号：KR100873824B1
公开(公告)日：2008-12-15
申请号：KR1020070043669
申请日：2007-05-04
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1008
Abstract: An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
Abstract translation: 错误控制码（ECC）设备可以包括基于信道信息生成ECC控制信号的控制信号生成器。 ECC设备还可以包括：多个ECC编码控制器，其输出经由对应于ECC控制信号的存储元件分别输入的数据; 和/或编码单元，其使用从所述多个ECC编码控制器输出的多个数据来编码输入数据到对应于所述ECC控制信号的多个子数据中。 另外或替代地，ECC设备可以包括：多个ECC解码控制器，其输出经由对应于ECC控制信号的存储元件分别输入的数据; 和/或解码单元，其使用从所述多个ECC解码控制器输出的多个数据将与所述ECC控制信号相对应的解码输入数据的数量解码为一个输出数据。
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公开(公告)号：KR1020080107921A
公开(公告)日：2008-12-11
申请号：KR1020070056317
申请日：2007-06-08
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/3418 , G11C16/3427
Abstract: An apparatus for programming a data of memory cell is provided to reduce error probability and the number of program by considering a floating poly coupling generated between memory cells. An apparatus for programming a data of memory cell is comprised of steps: calculating the change value of the threshold voltage based on source data of the memory cells(S430); converting source data programmed based on the change value of the calculated threshold voltage(S440); programming converted source data(S450). In especially calculating the change value of the threshold voltage, using the memory cells neighboring each other.
Abstract translation: 提供一种用于对存储器单元的数据进行编程的装置，以通过考虑在存储器单元之间产生的浮动多重耦合来减小误差概率和程序数量。 用于对存储单元的数据进行编程的装置包括以下步骤：基于存储器单元的源数据计算阈值电压的变化值（S430）; 转换基于所计算的阈值电压的变化值编程的源数据（S440）; 编程转换源数据（S450）。 特别是计算阈值电压的变化值时，使用彼此相邻的存储单元。
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公开(公告)号：KR1020080052288A
公开(公告)日：2008-06-11
申请号：KR1020070080179
申请日：2007-08-09
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1006 , G11C11/5621 , G11C16/06 , G11C29/38
Abstract: A multi-level cell memory device using concatenated coding is provided to store more than four bits in one memory cell by increasing the number of bits stored in one memory stably. A multi-level cell memory device includes an MLC(Multi Level Cell) memory cell(240), an outer encoder(210), an inner encoder(220) and a signal mapping module(230). The outer encoder generates outer encoded bit stream by encoding the data through first encoding method. The inner encoder generates inner encoded bit stream by encoding the outer encoded bit stream through second encoding method. The signal mapping module writes the data in the MLC memory cell by applying a program pulse according to the inner encoded bit stream to the MLC memory cell.
Abstract translation: 提供了使用级联编码的多级单元存储器件，用于通过增加存储在一个存储器中的比特数来稳定地存储在一个存储单元中的四位以上。 多级单元存储器件包括MLC（多级单元）存储单元（240），外编码器（210），内编码器（220）和信号映射模块（230）。 外部编码器通过第一编码方法对数据进行编码来生成外部编码比特流。 内部编码器通过第二编码方法对外部编码比特流进行编码来生成内部编码比特流。 信号映射模块通过根据内部编码比特流将编程脉冲施加到MLC存储器单元来将数据写入MLC存储器单元。
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Patent Agency Ranking
公开(公告)号：KR100822030B1
公开(公告)日：2008-04-15
申请号：KR1020060134049
申请日：2006-12-26
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/0483
Abstract: A multi-level cell memory device using high rate code is provided to minimize overhead of encoding and decoding as increasing the number of bits stored in one multi-level cell, by writing data in the multi-level cell memory through encoding of high code rate. A multi-level cell memory device storing data includes a groups of m-bit MLC(Multi-Level Cell) memory cells(261,262,263,264) where a and m are an integer above 2, an encoder(210) and a signal mapping part(220). The encoder generates encoded bit stream by encoding k bit data with code rate of k/n. The signal mapping part writes the encoded bit stream in the groups of m-bit MLC memory cells by applying a pulse according to the encoded bit stream to the group of m-bit MLC memory cells.
Abstract translation: 提供了一种使用高速码的多级信元存储装置，通过将多码单元存储器中的数据通过编码高码率进行写入，从而最小化编码和解码的开销，因为存储在一个多电平单元中的位数增加 。 存储数据的多级单元存储器件包括一组m位MLC（多级单元）存储单元（261,262,263,264），其中a和m是大于2的整数，编码器（210）和信号映射部分（220 ）。 编码器通过以k / n的码率对k位数据进行编码来生成编码比特流。 信号映射部分通过将编码的比特流应用到m比特MLC存储器单元组来将编码的比特流写入m比特MLC存储器单元的组中。
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公开(公告)号：KR101480383B1
公开(公告)日：2015-01-09
申请号：KR1020070074613
申请日：2007-07-25
Applicant: 삼성전자주식회사
CPC classification number: H03M13/235 , H03M13/6561
Abstract: 코드 인코딩/디코딩 장치 및 방법이 제공된다. 본 발명의 코드 인코딩 장치는 병렬적으로 p 비트의 입력 정보를 입력받아 클럭 주기에 따른 지연 정보를 생성하는 지연부 및 상기 입력 정보 또는 상기 지연 정보 중 적어도 하나에 기초하여 병렬적으로 nㆍp 비트의 코드를 생성하는 코드 생성부를 포함하며, 상기 n은 유리수이고, 이를 통해 간단한 회로 구성을 통해서도 코드 인코딩/디코딩 과정에 소요되는 시간을 단축할 수 있다.
convolutional code, concatenated code, 코드 인코딩, 코드 디코딩-
公开(公告)号：KR1020090075101A
公开(公告)日：2009-07-08
申请号：KR1020080000872
申请日：2008-01-03
Applicant: 삼성전자주식회사
CPC classification number: G06F11/141 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C29/00
Abstract: A memory device and an ECC(Error Control Code) decoding method are provided to improve the decoding performance by selectively applying the hard decision decoding or the soft decision decoding. A memory device(100) comprises a memory cell array(110), a decoder(120) and a controller(130). The decoder performs the hard decision decoding of first data and produces the output data and the error information of output data. The controller determines the bit error rate of output data based on the error information. If the bit error rate is greater than the target bit error rate, the controller transmits the additional read command for the soft decision decoding to the memory cell array. The memory cell array transmits the second data to the decoder when receives the additional read command. The decoder performs the soft decision decoding of second data and updates the output data.
Abstract translation: 提供存储器件和ECC（错误控制代码）解码方法，通过选择性地应用硬判决解码或软判决解码来提高解码性能。 存储器装置（100）包括存储单元阵列（110），解码器（120）和控制器（130）。 解码器执行第一数据的硬判决解码，并产生输出数据和输出数据的错误信息。 控制器根据错误信息确定输出数据的误码率。 如果误码率大于目标误码率，则控制器将用于软判决解码的附加读命令发送到存储单元阵列。 当接收附加读命令时，存储单元阵列将第二数据发送到解码器。 解码器执行第二数据的软判决解码并更新输出数据。
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公开(公告)号：KR1020090042108A
公开(公告)日：2009-04-29
申请号：KR1020070108026
申请日：2007-10-25
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C2211/5621
Abstract: An apparatus and method of a multi-bit programming in a multi-level memory device is provided to reduce reading failure by using a multi-level programming. A first controller(110) assigns one of 2^N bit threshold voltage states to N bit data. A first controller assigns one to 2^N threshold voltage to a data to be programmed the multi-bit cells respectively. A controller(120) assigns one to 2^N threshold voltage state by a first interval or a second interval. A second controller sets up interval between the second threshold voltage state and the first threshold voltage state the first. A programming part(130) form distribution corresponding to the allocated threshold voltage state is formed in the multi bit cell.
Abstract translation: 提供了一种在多级存储器件中进行多位编程的装置和方法，以通过使用多级编程来减少读取失败。 第一控制器（110）将2 ^ N位阈值电压状态中的一个分配给N位数据。 第一控制器分别向要编程的多位单元的数据分配1至2 N阈值电压。 控制器（120）以一个第一间隔或第二间隔分配一个至2N个阈值电压状态。 第二控制器设置第一阈值电压状态与第一阈值电压状态之间的间隔。 在多位单元中形成与所分配的阈值电压状态对应的编程部分（130）形式分布。
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公开(公告)号：KR1020090011230A
公开(公告)日：2009-02-02
申请号：KR1020070074613
申请日：2007-07-25
Applicant: 삼성전자주식회사
CPC classification number: H03M13/235 , H03M13/6561
Abstract: A device and a method for encoding/decoding codes in reduced time are provided to stably increase the number of bits stored in one memory cell and shorten the time needed for encoding/decoding an ECC(Error Correction Code) by applying a new error correction method to an MLC(Multi-Level Cell). A parallel BCH(Bose, Ray-Chaudhuri, Hocquenghem) code encoder(510) encodes external input information by using a BCH encoding technique. A parallel convolutional code encoder(520) generates an internal encoded bit stream by encoding an input information bit stream in an interleave convolutional encoding technique. A memory(550) stores the codes. A look-ahead Viterbi decoder(530) restores the input information by decoding the code in a look-ahead Viterbi decoding technique. A parallel BCH code decoder(540) restores the input information bit stream by decoding the internal encoded bit stream in a parallel Viterbi decoding technique.
Abstract translation: 提供一种用于在缩短时间内对代码进行编码/解码的装置和方法，以稳定地增加存储在一个存储单元中的位数，并通过应用新的纠错方法缩短对ECC（纠错码）进行编码/解码所需的时间 到MLC（多级单元）。 并行BCH（Bose，Ray-Chaudhuri，Hocquenghem）编码器（510）通过使用BCH编码技术对外部输入信息进行编码。 并行卷积码编码器（520）通过对交织卷积编码技术中的输入信息比特流进行编码来生成内部编码比特流。 存储器（550）存储代码。 先行维特比解码器（530）通过先行维特比解码技术中的代码解码来恢复输入信息。 并行BCH码解码器（540）通过以并行维特比解码技术解码内部编码比特流来恢复输入信息比特流。
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