公开(公告)号：KR1020140028618A

公开(公告)日：2014-03-10

申请号：KR1020120095223

申请日：2012-08-29

Applicant: 삼성전자주식회사

Inventor： 손종필 ,  박철우 ,  유학수 ,  황홍선

IPC: G11C7/10 ,  G11C8/08

CPC classification number: G06F3/061 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0676 ,  G06F3/068 ,  G06F13/1642 ,  G11C7/00 ,  G11C7/1048 ,  G11C11/4076 ,  Y02D10/14

Abstract: Disclosed are a memory device capable of reducing write failures, a memory system including the memory device, and a writing method thereof. The memory system of the present invention includes a memory device including a plurality of memory cells and a memory controller which controls the memory device. Data is written on selected memory cells of the memory device; write failures can be reduced by rewriting the data which was written right before the word line including the selected memory cells are pre-charged on the same selected memory cells. [Reference numerals] (AA) Start; (BB) End; (S110) Receive a write request and write data from a host; (S120) Store the write request in a write command queue and the write data in a data queue; (S130) Generate a series of command sequences according to the write request and apply a series of command sequences to a memory; (S140) After precharge, apply a rewrite command about data written right before precharge to the memory

Abstract translation: 公开了能够减少写入故障的存储器件，包括存储器件的存储器系统及其写入方法。 本发明的存储器系统包括一个包括多个存储器单元的存储器件和一个控制存储器件的存储器控​​制器。 数据写入存储器件的选定存储单元; 可以通过重写在包括所选存储单元的字线在预定的相同选定的存储单元之前写入的数据来减少写入失败。 （附图标记）（AA）开始; （BB）结束; （S110）从主机接收写入请求并写入数据; （S120）将写请求存储在写命令队列中，并将写数据存储在数据队列中; （S130）根据写请求生成一系列命令序列，并将一系列命令序列应用于存储器; （S140）预充电后，对预存的数据进行重写命令

公开(公告)号：KR1020140003223A

公开(公告)日：2014-01-09

申请号：KR1020120071241

申请日：2012-06-29

Applicant: 삼성전자주식회사

Inventor： 유학수 ,  박철우 ,  최주선

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/40607 ,  G06F3/0625 ,  G06F12/1009 ,  G06F2212/1028 ,  G11C11/40611 ,  G11C11/40622 ,  Y02D10/13

Abstract: Disclosed are a method for generating a DRAM address and a refresh power management system for reducing power consumed in a refresh operation. The method for generating the DRAM address for the refresh power management comprises generating an address corresponding to a memory area to be accessed among the memory areas of a DRAM, and generating the DRAM address to be transmitted to the DRAM by allocating to the address, a semantic code to be used for the DRAM power management.

Abstract translation: 公开了一种用于生成DRAM地址的方法和用于减少刷新操作中消耗的功率的刷新电源管理系统。 用于产生用于刷新功率管理的DRAM地址的方法包括：在DRAM的存储区域中生成与要访问的存储器区域对应的地址，并通过分配给地址生成要发送到DRAM的DRAM地址， 用于DRAM电源管理的语义代码。

公开(公告)号：KR101324192B1

公开(公告)日：2013-11-06

申请号：KR1020060091330

申请日：2006-09-20

Applicant: 삼성전자주식회사

Inventor： 박광성 ,  박철우

IPC: G06F1/26 ,  G06F3/12

CPC classification number: Y02D10/1592

Abstract: 본 발명은 프린팅장치 및 그 제어방법에 관한 것이다. 프린팅장치는, 프린팅을 수행하는 적어도 하나의 디바이스부와; 디바이스부를 제어하는 주제어부와; 주제어부에 전원을 공급하는 주전원부와; 사용자의 프린팅명령을 수신하는 명령수신부와; 주제어부보다 전력 소모가 작으며, 주제어부로의 전원 공급이 중지된 상태에서 명령수신부에 의해 프린팅명령이 수신되는 경우, 주제어부에 전원이 공급되도록 주전원부를 포함한다. 이에 의하여, 전력 소모를 감소시키며 동작의 신뢰성을 향상시킬 수 있다.

公开(公告)号：KR1020130066501A

公开(公告)日：2013-06-20

申请号：KR1020120118306

申请日：2012-10-24

Applicant: 삼성전자주식회사

Inventor： 김찬경 ,  이윤상 ,  박철우 ,  황홍선

IPC: G11C11/15 ,  G11C7/10

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/28 ,  G11C27/02 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06

Abstract: PURPOSE: A read or write operation method of a memory cell, an apparatus, and a memory system including the same are provided to improve the speed of write and read operations by quickening data as much as the writing speed of DRAM in a write operation and opening a page as the DRAM in a read operation. CONSTITUTION: A first switch(100) transmits data and selects a memory column. A second switch(300) is directly connected to a memory cell for data transmission and memory column selection. A sensing and storage circuit(200) is located between the first switch and the second switch and amplifies and stores the data. The memory cell is composed of resistive memory cells.

Abstract translation: 目的：提供存储单元，设备和包括该存储器单元的存储器系统的读或写操作方法，以通过在写入操作中加快DRAM的写入速度来提高写入和读取操作的速度，以及 在读操作中打开一个页面作为DRAM。 构成：第一开关（100）发送数据并选择存储器列。 第二开关（300）直接连接到用于数据传输和存储器列选择的存储单元。 感测和存储电路（200）位于第一开关和第二开关之间，并放大并存储数据。 存储单元由电阻式存储单元组成。

公开(公告)号：KR1020130027155A

公开(公告)日：2013-03-15

申请号：KR1020110090545

申请日：2011-09-07

Applicant: 삼성전자주식회사

Inventor： 김수아 ,  박철우 ,  김진호 ,  황홍선 ,  이상보

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/101 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/228 ,  H01L45/04

Abstract: PURPOSE: A semiconductor memory device is provided to implement high integration by vertically arranging a variable resistance pattern on an active pattern. CONSTITUTION: A plurality of active patterns are arranged on a substrate(100). The active pattern includes a first dopant region(105a), a channel region(103a), and a second dopant region(105b) which are vertically stacked. The channel region is formed between the first dopant region and the second dopant region. A gate pattern(120a) is formed on one sidewall of the active pattern. A gate dielectric pattern(110a) is formed between the gate pattern and the active pattern. A word line is connected to the gate pattern which is arranged in each row. A conductive pattern(120b) is formed on the other sidewall of the active pattern.

Abstract translation: 目的：提供半导体存储器件以通过在活动图案上垂直布置可变电阻图案来实现高集成度。 构成：在衬底（100）上布置多个有源图案。 有源图案包括垂直堆叠的第一掺杂区域（105a），沟道区域（103a）和第二掺杂区域（105b）。 沟道区形成在第一掺杂区和第二掺杂区之间。 栅极图案（120a）形成在有源图案的一个侧壁上。 在栅极图案和活性图案之间形成栅极电介质图案（110a）。 字线连接到布置在每一行中的栅极图案。 导电图案（120b）形成在有源图案的另一个侧壁上。

公开(公告)号：KR1020130026973A

公开(公告)日：2013-03-14

申请号：KR1020120049775

申请日：2012-05-10

Applicant: 삼성전자주식회사

Inventor： 유학수 ,  강욱성 ,  박철우 ,  최주선 ,  황홍선

IPC: G11C29/00

CPC classification number: G11C29/70 ,  G11C29/10 ,  G11C29/787 ,  G11C2229/763

Abstract: PURPOSE: A memory system is provided to improve the reliability of an SRAM by scrubbing the SRAM in a DRAM refresh cycle. CONSTITUTION: A first memory region includes a plurality of memory cells. A test unit(10) tests the first memory region and detects a weak bit among a plurality of memory cells. A second memory region(30) stores a weak bit address of the first memory region and data stored in the weak bit address. The first memory region and the second memory region are composed of different kinds of memory cells.

Abstract translation: 目的：提供一种存储系统，通过在DRAM刷新周期中擦除SRAM来提高SRAM的可靠性。 构成：第一存储区包括多个存储单元。 测试单元（10）测试第一存储器区域并检测多个存储器单元中的弱位。 第二存储器区域（30）存储第一存储区域的弱位地址和存储在弱位地址中的数据。 第一存储区域和第二存储器区域由不同种类的存储单元组成。

公开(公告)号：KR1020120136674A

公开(公告)日：2012-12-20

申请号：KR1020110055744

申请日：2011-06-09

Applicant: 삼성전자주식회사

Inventor： 강욱성 ,  유학수 ,  박철우

IPC: G11C29/42 ,  G11C11/403

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/106 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: PURPOSE: An on-chip data scrubbing apparatus including an error correcting circuit and a scrubbing method thereof are provided to prevent the accumulation of error over a single bit by a scrubbing refresh operation. CONSTITUTION: A command decoder(3300) generates an inner control signal by decoding a command. An error correcting circuit(3500) detects and corrects errors about read data of a memory array. A scrubbing refresh managing unit(3700) activates a page of the memory array in response to a first command and selects a sub page of the activated page. A scrubbing refresh managing unit rewrites the error corrected data in a sub page according to the error detection result of the selected sub page.

Abstract translation: 目的：提供包括错误校正电路及其擦除方法的片上数据擦除装置，以通过擦洗刷新操作来防止错误在单个位上的累积。 构成：命令解码器（3300）通过对命令进行解码来生成内部控制信号。 误差校正电路（3500）检测和校正关于存储器阵列的读取数据的错误。 擦洗刷新管理单元（3700）响应于第一命令激活存储器阵列的页面并选择激活的页面的子页面。 擦洗刷新管理单元根据所选子页的错误检测结果重写子页中的纠错数据。

公开(公告)号：KR1020120095226A

公开(公告)日：2012-08-28

申请号：KR1020110014766

申请日：2011-02-18

Applicant: 삼성전자주식회사

Inventor： 유학수 ,  김수아 ,  황홍선 ,  박철우

IPC: G11C7/12 ,  G11C7/06 ,  G11C8/08

CPC classification number: G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

Abstract: PURPOSE: A memory core and a semiconductor memory device including the same are provided to decrease a chip area by removing a dummy bit line and an edge block. CONSTITUTION: A memory core(100) includes a memory array block and a bit line sense amplifier. A memory array block(120,140,160) includes a plurality of rows and columns comprising memory cells with cell access transistors, a first word line, and a second word line. The first word line is arranged on the upper side of the cell access transistor of the plurality of columns. The second word line is arranged on the lower side of the cell access transistor. A bit line sense amplifier(110,130,150,170) amplifies a voltage difference between two bit lines arranged in the memory array block.

Abstract translation: 目的：提供包括其的存储器芯和半导体存储器件，以通过去除虚拟位线和边沿块来减小芯片面积。 构成：存储器芯（100）包括存储器阵列块和位线读出放大器。 存储器阵列块（120,140,​​160）包括多个行和列，包括具有单元存取晶体管的存储单元，第一字线和第二字线。 第一字线布置在多列的单元存取晶体管的上侧。 第二字线布置在单元存取晶体管的下侧。 位线读出放大器（110,130,150,170）放大布置在存储器阵列块中的两个位线之间的电压差。

公开(公告)号：KR1020120043314A

公开(公告)日：2012-05-04

申请号：KR1020100104553

申请日：2010-10-26

Applicant: 삼성전자주식회사

Inventor： 박철우 ,  백인규 ,  손동현 ,  황홍선

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/79 ,  G11C5/14 ,  G11C7/20 ,  G11C13/0002

Abstract: PURPOSE: A resistive memory device, an initializing method thereof, and electronic devices including the same are provided to rapidly initialize a resistive memory cell by using an initialization path formed along a voltage supplied from the outside of the resistive memory device. CONSTITUTION: A first pad(PAD1) supplies a first voltage supplied from the outside to a first plate in an initialization operation. A second pad(PAD2) supplies a second voltage from the outside to a second plate in an initialization operation. A first transistor includes a gate, a drain, and a source connected to a first plate. A first memory resistor is connected between a bit line and the drain of the first transistor. A second transistor includes a gate, a drain, and a source connected to a second plate. A second memory resistor is connected between a bit line and the drain of the second transistor.

Abstract translation: 目的：提供一种电阻式存储器件及其初始化方法以及包括该电阻式存储器件的电子器件，通过使用沿着从电阻式存储器件的外部提供的电压形成的初始化路径来快速初始化电阻性存储器单元。 构成：在初始化操作中，第一焊盘（PAD1）将从外部提供的第一电压提供给第一板。 在初始化操作中，第二焊盘（PAD2）从外部向第二板提供第二电压。 第一晶体管包括连接到第一板的栅极，漏极和源极。 第一存储电阻器连接在位线和第一晶体管的漏极之间。 第二晶体管包括连接到第二板的栅极，漏极和源极。 第二存储电阻连接在位线和第二晶体管的漏极之间。

公开(公告)号：KR1020120037528A

公开(公告)日：2012-04-20

申请号：KR1020100099034

申请日：2010-10-12

Applicant: 삼성전자주식회사

Inventor： 김수아 ,  박철우 ,  황홍선 ,  유학수

IPC: G11C11/4091 ,  G11C11/4099 ,  G11C7/12 ,  G11C7/06 ,  G11C8/08

CPC classification number: G11C11/4091 ,  G11C11/4099 ,  G11C5/14 ,  G11C7/06 ,  G11C7/065 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4094

Abstract: PURPOSE: A semiconductor memory device for sensing data is provided to improve the operation reliability of a memory device by enhancing data sensing margin. CONSTITUTION: A main cell(20) is arranged in an intersection between a word line and a bit line. A reference cell is arranged in an intersection between a reference word line and a bit line bar. A bit line sensing amplifier(22) senses and amplifies data transmitted through a bit line and a pair of bit line bars. A gate of a first switching transistor(T1) is controlled by the word line and a drain thereof is connected to the bit line. The main capacitor is connected between a source of a switching transistor and a main plate voltage. A gate of a second switching transistor is controlled by the reference word line and a drain thereof is connected to the bit line bar. A reference capacitor(C2) is connected between a source of the switching transistor and a reference plate voltage.

Abstract translation: 目的：提供一种用于感测数据的半导体存储器件，通过增强数据传感裕度来提高存储器件的操作可靠性。 构成：主单元（20）布置在字线和位线之间的交点中。 参考单元布置在参考字线和位线条之间的交叉点中。 位线感测放大器（22）感测并放大通过位线和一对位线条传输的数据。 第一开关晶体管（T1）的栅极由字线控制，其漏极连接到位线。 主电容器连接在开关晶体管的源极和主板电压之间。 第二开关晶体管的栅极由参考字线控制，其漏极连接到位线条。 参考电容器（C2）连接在开关晶体管的源极和基准电压之间。