公开(公告)号：KR1020140042459A

公开(公告)日：2014-04-07

申请号：KR1020120109255

申请日：2012-09-28

Applicant: 삼성전자주식회사

Inventor： 이충기 ,  황홍선 ,  권형신 ,  임종형

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/00

CPC classification number: H01L27/088 ,  G11C11/40 ,  G11C11/404 ,  G11C11/4085 ,  G11C11/4094 ,  G11C2207/005 ,  H01L27/10897

Abstract: The present invention relates to a multiple well bias memory device. A memory device includes a semiconductor substrate, a first wall of a first conductivity type where a memory cell is formed on the semiconductor substrate, and a second wall of a first conductivity type where a sensor amplifier of sensing and amplifying the data of the memory cell is formed in the semiconductor substrate. The doping concentration of the first wall is different from that of the second wall. The first wall is biased with a first voltage. The second wall is biased with a second voltage which is different from the first voltage. The first voltage is lower than the second voltage.

Abstract translation: 本发明涉及多阱偏压存储器件。 存储器件包括半导体衬底，在半导体衬底上形成存储单元的第一导电类型的第一壁和第一导电类型的第二壁，其中感测和放大存储单元的数据的传感器放大器 形成在半导体衬底中。 第一壁的掺杂浓度不同于第二壁的掺杂浓度。 第一个墙壁被第一个电压偏置。 第二壁用与第一电压不同的第二电压进行偏置。 第一电压低于第二电压。

公开(公告)号：KR1020080040207A

公开(公告)日：2008-05-08

申请号：KR1020060107857

申请日：2006-11-02

Applicant: 삼성전자주식회사

Inventor： 손상기 ,  임종형

IPC: G11C8/10 ,  G11C8/12 ,  G11C8/18

Abstract: A semiconductor memory device is provided to increase the reliability of the semiconductor memory device by reducing the time for a PMOS transistor comprised in a NAND gate to receive stress due to high electric field. A memory cell array comprises a plurality of memory cell array blocks comprising a plurality of memory cells accessed in response to a word line enable signal enabling a plurality of main word lines. An auto pulse generation circuit(152) receives a plurality of block enabling signals to select the plurality of memory cell array blocks, and outputs a block signal enabled if a corresponding block enabling signal is disabled and then disabled after a fixed time. A row decoder precharges the main word line in response to the enabled block signal, and comprises a plurality of main word line drivers outputting the word line enable signal in response to an address.

Abstract translation: 提供半导体存储器件以通过减少包括在NAND门中的PMOS晶体管的时间来接收由于高电场引起的应力而增加半导体存储器件的可靠性。 存储单元阵列包括多个存储单元阵列块，所述多个存储单元阵列块包括响应于启用多个主字线的字线使能信号而被访问的多个存储单元。 自动脉冲发生电路（152）接收多个块使能信号以选择多个存储单元阵列块，并且如果相应的块使能信号被禁用然后在固定时间后禁用，则输出启用的块信号。 行解码器响应于使能的块信号对主字线进行预充电，并且包括响应于地址而输出字线使能信号的多个主字线驱动器。

公开(公告)号：KR100800382B1

公开(公告)日：2008-02-01

申请号：KR1020060077400

申请日：2006-08-17

Applicant: 삼성전자주식회사

Inventor： 임종형 ,  강상석

IPC: G11C11/40 ,  G11C7/20

CPC classification number: G11C7/1078 ,  G11C7/1006 ,  G11C7/1096 ,  G11C11/4096 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

Abstract: A method for signal control in a semiconductor memory device and a circuit for generating a CSL(Column Selection Line) enable signal therefore are provided to assure sufficient mask margin by controlling data and a data mask signal with two clock signals respectively. According to a method for signal control in a semiconductor memory device, a data signal and a data mask signal are controlled to have different internal latency during write operation. The data mask signal latency is shorter than data latency of the data signal. The data latency is delay time before data is inputted after a write command signal is generated, and the data mask signal latency is delay time before the data mask signal is inputted after the write command signal is generated. The latency control is performed by inputting the data mask signal earlier than the data or reducing delay time.

Abstract translation: 提供半导体存储器件中的信号控制方法和用于产生CSL（列选择线）使能信号的电路，以通过分别通过两个时钟信号控制数据和数据屏蔽信号来确保足够的掩模余量。 根据半导体存储器件中的信号控制方法，数据信号和数据掩模信号被控制为在写入操作期间具有不同的内部等待时间。 数据掩码信号延迟比数据信号的数据延迟更短。 数据等待时间是在产生写入命令信号之后输入数据之前的延迟时间，并且数据屏蔽信号等待时间是在产生写入命令信号之后输入数据屏蔽信号之前的延迟时间。 延迟控制是通过比数据早的输入数据掩码信号或减少延迟时间来执行的。

公开(公告)号：KR1020070030627A

公开(公告)日：2007-03-16

申请号：KR1020050085431

申请日：2005-09-13

Applicant: 삼성전자주식회사

Inventor： 임종형 ,  강상석 ,  정용환 ,  변상만

IPC: G11C29/00

CPC classification number: G11C17/18

Abstract: 본 발명은 퓨즈 회로를 구비한 반도체 장치를 공개한다. 이 장치는 파워 업 신호에 응답하여 제1노드로 제1신호를 발생하는 제1신호 발생기, 제1신호에 응답하여 제2노드를 풀다운하는 풀다운 트랜지스터, 전원전압과 제2노드사이에 직렬 연결되고 컷팅이 되지 않았으면 제1신호에 응답하여 제2노드를 풀업하는 풀업 트랜지스터와 퓨즈, 제2노드의 신호를 버퍼하여 제어신호를 발생하는 버퍼, 및 버퍼의 출력신호에 응답하여 제2노드를 리셋하는 스탠바이 리셋 트랜지스터를 구비하며, 풀다운 트랜지스터 및 스탠바이 리셋 트랜지스터의 문턱전압이 버퍼의 문턱전압에 비해서 낮은 문턱전압을 가지는 것을 특징으로 하는 복수개의 퓨즈 회로들로 구성되어 있다. 또한, 액티브시에 제2노드를 리셋하는 액티브 리셋 트랜지스터가 추가되어 구성되어 있다. 따라서, 퓨즈가 컷팅되지 않은 경우에 발생될 수 있는 원하지 않는 누설 전류를 제거할 수 있음은 물론, 퓨즈가 컷팅된 경우에 제어신호의 상태가 변화되는 것을 방지할 수 있다.

公开(公告)号：KR100666617B1

公开(公告)日：2007-01-10

申请号：KR1020050071655

申请日：2005-08-05

Applicant: 삼성전자주식회사

Inventor： 변상만 ,  강상석 ,  임종형

IPC: G11C7/06 ,  G11C11/4063

CPC classification number: G11C11/4091 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/002

Abstract: A bit line sense amplifier and a semiconductor memory device having the same are provided to prevent voltages applied on a bit line pair from being decreased by using a bit line voltage compensation circuit. A bit line sense amplifier includes sense amplifiers(15,16), a source voltage supply circuit, and a bit line voltage compensation circuit(20). The sense amplifiers are coupled between first and second bit lines and increase the voltage difference between the first and second bit lines. The source voltage supply circuit supplies first and second source voltages to the sense amplifiers in response to a bit line sensing control signal. The bit line voltage compensation circuit supplies a third source voltage, which is different from the first and second source voltages, to the sense amplifiers in response to the bit line sensing control signal and a sensing enable signal, so that the voltages applied on the first and second bit lines are maintained at a constant value by a predetermined time after a bit line precharge process.

Abstract translation: 提供有位线读出放大器和具有该位线读出放大器的半导体存储器件，以通过使用位线电压补偿电路来防止施加在位线对上的电压减小。 位线读出放大器包括读出放大器（15,16），源极电压供应电路和位线电压补偿电路（20）。 读出放大器耦合在第一和第二位线之间并且增加第一和第二位线之间的电压差。 源电压供应电路响应于位线检测控制信号向读出放大器提供第一和第二源电压。 位线电压补偿电路响应于位线感测控制信号和感测使能信号，将不同于第一和第二源电压的第三源电压提供给读出放大器，使得施加在第一 并且在位线预充电处理之后的预定时间将第二位线维持在恒定值。

公开(公告)号：KR1020060053583A

公开(公告)日：2006-05-22

申请号：KR1020040093995

申请日：2004-11-17

Applicant: 삼성전자주식회사

Inventor： 임종형 ,  박광일

IPC: G11C5/14

CPC classification number: G05F1/575

Abstract: A reference voltage generator generates an output reference voltage having various voltage levels. The reference voltage generator includes an amplifier to amplify a difference between a feedback reference voltage and a feedback voltage to generate an amplified signal, a current driving circuit to provide a current signal in response to the amplified signal, a scaler circuit to generate feedback voltage signals and reference voltage signals in response to the current signal, and a feedback voltage selecting circuit to select one of the feedback voltage signals in response to a control signal, and to provide the selected feedback voltage signal to the operational amplifier as the feedback voltage.

公开(公告)号：KR100532423B1

公开(公告)日：2005-11-30

申请号：KR1020030013427

申请日：2003-03-04

Applicant: 삼성전자주식회사

Inventor： 김신호 ,  임종형

IPC: G11C7/10

Abstract: 뱅크별로 데이터 라인의 부하 차이에 기인하는 스큐를 제거할 수 있는 기입 드라이버를 구비하는 반도체 메모리장치 및 이의 스큐 제거방법이 개시된다. 상기 반도체 메모리장치는, 복수개의 메모리 뱅크들; 상기 뱅크들에 공유되어 사용되는 데이터 라인; 기입동작시 외부에서 입력되는 데이터를 받아 상기 데이터 라인을 구동하는 기입 드라이버를 구비하고, 상기 기입 드라이버는 뱅크별로 상기 데이터 라인의 부하 차이에 기인하는 스큐를 제거하기 위해, 뱅크 정보에 응답하여 상기 데이터를 지연없이 받아 상기 데이터 라인을 구동하거나 또는 상기 데이터를 소정의 시간만큼 지연시킨 후 받아 상기 데이터 라인을 구동하는 것을 특징으로 한다.

公开(公告)号：KR100434482B1

公开(公告)日：2004-07-16

申请号：KR1019970041584

申请日：1997-08-27

Applicant: 삼성전자주식회사

Inventor： 임종형 ,  강상석 ,  조강용 ,  김홍범

IPC: G11C7/06

Abstract: PURPOSE: A split gate control circuit and a control method thereof and a semiconductor memory device using the same are provided to improve sensing and amplification speed of a bit line sense amplifier. CONSTITUTION: A memory cell array(301) includes a number of memory cells. A split gate unit(303) transfers a voltage of a bit line and a complementary bit line of the memory cell array in response to a split gate control signal. A sense amplifier(305) senses and amplifies a potential difference between the bit line and the complementary bit line. A sense amplifier enable unit(309) enables the sense amplifier in response to a sense amplifier control signal. The first logic gate(307a) performs an AND operation of decoded row addresses to select the split gate unit. A pulse generation unit(307b) generates a pulse by receiving the sense amplifier control signal. And the second logic gate(307c) generates the split gate control signal by performing an AND operation of the output of the first logic gate and the output of the pulse generation unit.

公开(公告)号：KR100292404B1

公开(公告)日：2001-06-01

申请号：KR1019980001426

申请日：1998-01-19

Applicant: 삼성전자주식회사

Inventor： 임종형 ,  강상석

IPC: G11C7/00

Abstract: PURPOSE: A dual-purpose transfer circuit and a dual-purpose input method using the same are provided to reduce the number of pads by at least two signals or at least two voltages into one pad. CONSTITUTION: A transfer circuit included in a semiconductor device having at least one input pad(30) includes an inner signal line for transmitting a signal to the semiconductor device, an inner voltage line for transmitting a signal to the semiconductor device, a first transfer circuit(31) for making the input pad(30) be communicated with the inner signal line according to a predetermined control signal at a normal input mode, and a second transfer circuit(33) for making the input pad(30) be communicated with the inner voltage line according to the control signal at a voltage input mode. A buffer buffers a signal transferred by the first transfer circuit(31), and outputs the buffered signal to the inner signal line.

公开(公告)号：KR1020000074816A

公开(公告)日：2000-12-15

申请号：KR1019990019024

申请日：1999-05-26

Applicant: 삼성전자주식회사

Inventor： 노영실 ,  임종형 ,  김경무

IPC: G05F1/10

Abstract: PURPOSE: A boosting voltage detecting device is provided to prevent a boosting potential from being increased excessively at a burn-in test mode by diversifying a boosting voltage detection level at normal operation and burn-in test mode. CONSTITUTION: A boosting voltage detecting device comprises a voltage dividing part(30), a resistance adjusting part(37) and inverters(31,33,35,39). The voltage dividing part(30) consists of the first resistance portion(MN30-MN34) and the second resistance portion(MN35-MN41), and divides a power supply voltage according to a resistance ratio of the first and second resistance portions. The resistance adjusting part(37) is connected in parallel with the second resistance portion of the voltage dividing part(30), and adjusts a resistance of the second resistance portion at a burn-in test mode. The inverters(31,33,35,39) are connected in series to a connection node between the first and second resistance portions, and outputs a boosting potential detection signal(PDETPP) according to the potential level of the connection node.

Abstract translation: 目的：提供一种升压电压检测装置，用于通过在正常操作和老化测试模式下使升压电压检测电平多样化来防止在老化测试模式下过度增加升压电位。 构成：升压电压检测装置包括分压部（30），电阻调节部（37）和逆变器（31,33,35,39）。 分压部（30）由第一电阻部（MN30-MN34）和第二电阻部（MN35-MN41）构成，并且根据第一和第二电阻部的电阻比分割电源电压。 电阻调节部（37）与分压部（30）的第二电阻部并联连接，并且在老化试验模式下调整第二电阻部的电阻。 逆变器（31,33,35,39）与第一和第二电阻部分之间的连接节点串联连接，并根据连接节点的电位电平输出升压电位检测信号（PDETPP）。