公开(公告)号：KR1020030057947A

公开(公告)日：2003-07-07

申请号：KR1020010088063

申请日：2001-12-29

Applicant: 삼성전자주식회사

Inventor： 전정식 ,  지경구 ,  강창진 ,  함진환

IPC: H01L27/04

CPC classification number: H01L27/10852 ,  H01L21/76895 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

Abstract: PURPOSE: A method for fabricating a cylindrical capacitor of a semiconductor device is provided to reduce step coverage between hard mask patterns of a cell array region and a peripheral circuit region by performing an etch-back process for a hard mask pattern. CONSTITUTION: An etch stopper layer and a mold layer are formed on a semiconductor substrate(100) including a plug formed within a buried contact hole. A hard mask pattern is formed on the mold layer. A mold pattern and an etch stopper layer pattern(125a) are formed by etching the mold layer and the etch stopper layer. The step coverage between hard mask patterns is reduced by etching back the hard mask pattern. A conductive layer for capacitor bottom electrode is formed on an inner wall of the buried contact hole and a surface of the mold pattern. A sacrificial layer is formed between the buried contact hole and the mold pattern. A capacitor bottom electrode(133a) is formed by etching back the conductive layer. The mold pattern and the sacrificial layer are removed.

Abstract translation: 目的：提供一种用于制造半导体器件的圆柱形电容器的方法，以通过对硬掩模图案执行回蚀处理来减小单元阵列区域的硬掩模图案与外围电路区域之间的步骤覆盖。 构成：在包括形成在埋入接触孔内的插塞的半导体衬底（100）上形成蚀刻停止层和模制层。 在模具层上形成硬掩模图案。 通过蚀刻模具层和蚀刻停止层来形成模具图案和蚀刻停止层图案（125a）。 通过蚀刻硬掩模图案来减少硬掩模图案之间的台阶覆盖。 用于电容器底部电极的导电层形成在埋入接触孔的内壁和模具图案的表面上。 在掩埋接触孔和模具图案之间形成牺牲层。 通过蚀刻导电层形成电容器底部电极（133a）。 去除模具图案和牺牲层。

公开(公告)号：KR1020020045028A

公开(公告)日：2002-06-19

申请号：KR1020000074317

申请日：2000-12-07

Applicant: 삼성전자주식회사

Inventor： 전정식 ,  민경진 ,  박완재 ,  지경구

IPC: H01L27/10

CPC classification number: H01L21/76831 ,  H01L21/76877 ,  H01L21/76897

Abstract: PURPOSE: A method for manufacturing a semiconductor device capable of forming a pad without void in performing a self-align contact etch processing is provided to prevent an undercut and a void by forming passivation spacers. CONSTITUTION: A conductive pattern(18) made of a gate insulating layer(12), a gate electrode(14) and a capping layer(16) is formed on a substrate(10). Then, an interlayer dielectric is formed on the resultant structure. After mask pattern is formed on the interlayer dielectric, an interlayer dielectric pattern(22a) having a contact hole for the exposure of the substrate(10) is formed by a self-align contact etch of the interlayer dielectric using the mask pattern as an etch mask. Passivation spacers(32a) are formed on both sidewalls of the mask pattern and the interlayer dielectric pattern(22a), thereby preventing the undercut on the contact surface between the mask pattern and the interlayer dielectric pattern(22a). A conductive layer for pad is formed on the entire surface of the resultant structure so as to fill up the contact hole. At this time, no void is formed. A pad(34a) buried into the contact hole is formed by planarizing the conductive layer for pad.

Abstract translation: 目的：提供一种能够在进行自对准接触蚀刻处理时能够形成无空隙的衬底的半导体器件的制造方法，以通过形成钝化间隔物来防止底切和空隙。 构成：在基板（10）上形成由栅极绝缘层（12），栅电极（14）和覆盖层（16）构成的导体图案（18）。 然后，在所得结构上形成层间电介质。 在层间电介质上形成掩模图案之后，通过使用掩模图案作为蚀刻的层间电介质的自对准接触蚀刻形成具有用于曝光基板（10）的接触孔的层间电介质图案（22a） 面具。 钝化间隔物（32a）形成在掩模图案和层间电介质图案（22a）的两个侧壁上，从而防止掩模图案和层间电介质图案（22a）之间的接触表面上的底切。 在所得结构的整个表面上形成用于焊盘的导电层，以便填充接触孔。 此时，没有空隙形成。 通过平坦化用于焊盘的导电层来形成埋入接触孔中的焊盘（34a）。

公开(公告)号：KR1020020041224A

公开(公告)日：2002-06-01

申请号：KR1020000071033

申请日：2000-11-27

Applicant: 삼성전자주식회사

Inventor： 박완재 ,  민경진 ,  전정식

IPC: H01L21/316

CPC classification number: H01L21/31144 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/31138 ,  H01L21/3125 ,  H01L21/76837

Abstract: PURPOSE: A formation method of an interlayer dielectric is provided to fill a gap between conductive lines without a void or a crack by a dry etch-back using a defined etching gas between a baking processing and a thermal treatment. CONSTITUTION: Conductive lines(106) layered with a conductive layer(102) and a hard mask(104) are formed on a substrate(100). Then, a SOG(Spin On Glass)(108) of a polysilazane system is deposited on the entire surface of the resultant structure. The SOG(108) is baked by two-step processing and is then etched to expose the upper surface of the conductive lines(106) with an etching gas. At this time, the etching gas composed of carbon and fluorine elements has over 0.5 in the ratio of C/F. A silicon oxide is formed by performing a thermal treatment on the residual SOG(108).

Abstract translation: 目的：提供层间电介质的形成方法，以在烘烤处理和热处理之间使用限定的蚀刻气体，通过干蚀刻来填充导线之间的间隙而没有空隙或裂纹。 构成：在基板（100）上形成层叠有导电层（102）和硬掩模（104）的导电线（106）。 然后，将聚硅氮烷系统的SOG（旋转玻璃）（108）沉积在所得结构的整个表面上。 SOG（108）通过两步处理进行烘烤，然后进行蚀刻以用蚀刻气体暴露导电线（106）的上表面。 此时，由碳氟元素构成的蚀刻气体以C / F的比例超过0.5。 通过对剩余的SOG（108）进行热处理来形成氧化硅。

公开(公告)号：KR1020020039461A

公开(公告)日：2002-05-27

申请号：KR1020000069287

申请日：2000-11-21

Applicant: 삼성전자주식회사

Inventor： 이성춘 ,  민경진 ,  전정식 ,  신경섭

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76897 ,  H01L27/10894

Abstract: PURPOSE: A method for fabricating a semiconductor device comprising contact studs of various kinds is provided to simply a total process by overcoming reduction of a design rule and increase of a stepped portion between a core region and a peripheral region. CONSTITUTION: A bit line(510) is formed on a semiconductor substrate(100). The second spacer layer is formed on the bit line(510). The second spacer(591) and the first etch stop pattern(595) are formed thereon. A lower electrode(710), a dielectric layer(730), and an upper electrode layer are formed on a conductive pad(410). An upper electrode(751) is formed by patterning the upper electrode layer. The thickness of the second capping layer is reduced by performing an etch process. The fourth interlayer dielectric(370) is formed on the upper electrode(751). A multitude of contact hole is formed thereon. The first etch stop pattern(595) and the second etch stop pattern(555) exposed by the contact hole are removed. A multitude of conductive stud(815,835,855,875) is formed.

Abstract translation: 目的：通过克服设计规则的减少和芯区域与周边区域之间的阶梯部分的增加，提供了包括各种接触螺柱的半导体器件的制造方法，以简单地实现整个工艺。 构成：位线（510）形成在半导体衬底（100）上。 第二间隔层形成在位线（510）上。 在其上形成第二间隔物（591）和第一蚀刻停止图案（595）。 在导电焊盘（410）上形成下电极（710），电介质层（730）和上电极层。 通过图案化上电极层形成上电极（751）。 通过执行蚀刻工艺来减小第二覆盖层的厚度。 第四层间电介质（370）形成在上电极（751）上。 在其上形成多个接触孔。 去除由接触孔露出的第一蚀刻停止图案（595）和第二蚀刻停止图案（555）。 形成多个导电螺柱（815,835,855,875）。

公开(公告)号：KR1020020033881A

公开(公告)日：2002-05-08

申请号：KR1020000064054

申请日：2000-10-30

Applicant: 삼성전자주식회사

Inventor： 전정식 ,  김재웅

IPC: H01L21/28

CPC classification number: H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A method for fabricating a semiconductor device having a contact hole is provided to prevent damage to a semiconductor substrate, by using a dry etch process and a wet etch process to eliminate an insulation layer in forming the contact hole penetrating the insulation layer on the semiconductor substrate. CONSTITUTION: A lower insulation layer is formed on the semiconductor substrate(101). An upper insulation layer is formed on the lower insulation layer. The upper insulation layer and the lower insulation layer are anisotropically etched to form a trench(119) which penetrates the upper insulation layer and has a depth shallower than the sum of the thickness of the lower insulation layer and the upper insulation layer. The lower insulation layer exposed by the trench is isotropically etched to form a contact hole of which the lower portion has a wider width than the upper portion.

Abstract translation: 目的：提供一种用于制造具有接触孔的半导体器件的方法，以通过使用干蚀刻工艺和湿蚀刻工艺来消除半导体衬底的损坏，以消除在形成穿过绝缘层的接触孔的绝缘层 半导体衬底。 构成：在半导体衬底（101）上形成下绝缘层。 上绝缘层形成在下绝缘层上。 上绝缘层和下绝缘层被各向异性地蚀刻以形成穿透上绝缘层并且具有比下绝缘层和上绝缘层的厚度之和更深的沟槽（119）。 由沟槽露出的下绝缘层被各向同性地蚀刻以形成其下部具有比上部宽的宽度的接触孔。

公开(公告)号：KR1020000009277A

公开(公告)日：2000-02-15

申请号：KR1019980029554

申请日：1998-07-22

Applicant: 삼성전자주식회사

Inventor： 전정식 ,  유병덕

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a contact hole in a semiconductor memory device is provided to reduce a maximum size of the contact hole, so that a short between the embedded contact and a neighbor conductive film is prevented. CONSTITUTION: According to the forming method, an etching process is performed to an insulation film(104) where a conductive film is formed by a mask of photoresist film pattern(112), so that a hole(114) whose depth is deeper than a width of the conductive film is formed. Next, A side-wall insulation film(116) is formed in the formed hole(114). Last, the hole(114) where the side-wall insulation film(116) is formed is etched deeply with a maximum depth, so that a contact hole(118) is formed. Thereby, the maximum size of the contact hole(118) can be reduced by the side-wall insulation film(116).

Abstract translation: 目的：提供一种在半导体存储器件中形成接触孔的方法，以减小接触孔的最大尺寸，从而防止嵌入触点和相邻导电膜之间的短路。 构成：根据该形成方法，对通过光致抗蚀剂膜图案（112）的掩模形成导电膜的绝缘膜（104）进行蚀刻处理，使得深度比深度深的孔（114） 形成导电膜的宽度。 接下来，在成形孔（114）中形成侧壁绝缘膜（116）。 最后，形成侧壁绝缘膜（116）的孔（114）以最大深度深度地蚀刻，从而形成接触孔（118）。 由此，可以通过侧壁绝缘膜（116）来减小接触孔（118）的最大尺寸。

公开(公告)号：KR1020000009276A

公开(公告)日：2000-02-15

申请号：KR1019980029553

申请日：1998-07-22

Applicant: 삼성전자주식회사

Inventor： 박완재 ,  전정식 ,  최성길

IPC: H01L21/306

Abstract: PURPOSE: The method is to settle electric short problem of capacitor and prevent falling off of uniformity of the capacitor. CONSTITUTION: On top of an aluminum film(100) acting as lower conductive film, a titanium nitride(102) and an interlayer insulation film(104) are formed. Then, mask layer is formed by use of photosensitive layer. Thereafter, the titanium nitride and interlayer insulation film are patterned by accomplishing etching process through the mask layer. In accomplishing etching process for patterning titanium nitride and interlayer insulation film formed on top of aluminum film, the etching method uses etching agent having high C4F8 and oxygen ratio to increase etching selection ratio between the titanium nitride and the interlayer insulation film. As a result, since titanium nitride remains on top of the aluminum film when etching is made, the problem of electric short of capacitor can be settled and uniformity of capacitance is improved.

Abstract translation: 目的：解决电容器短路问题，防止电容器均匀性下降。 构成：在作为下导电膜的铝膜（100）的顶部，形成氮化钛（102）和层间绝缘膜（104）。 然后，通过使用感光层形成掩模层。 此后，通过通过掩模层的蚀刻工艺对氮化钛和层间绝缘膜进行图案化。 在完成形成在铝膜顶部的氮化钛和层间绝缘膜的蚀刻工艺中，蚀刻方法使用具有高C4F8和氧比的蚀刻剂来提高氮化钛和层间绝缘膜之间的蚀刻选择比。 结果，由于当进行蚀刻时，由于氮化钛保留在铝膜的顶部，所以能够稳定电容器的短路的问题，提高电容的均匀性。

公开(公告)号：KR1020000008736A

公开(公告)日：2000-02-15

申请号：KR1019980028687

申请日：1998-07-15

Applicant: 삼성전자주식회사

Inventor： 전정식 ,  안태혁 ,  황재성

IPC: H01L21/28

Abstract: PURPOSE: A silicide ion re-coating prevention method in manufacturing process of semiconductor device is provided to prevent the inside adhesion or re-coating of silicide ion when a metal silicide layer is etched in a contact hole formation process for a semiconductor device. CONSTITUTION: The present invention discloses a silicide ion re-coating prevention method in manufacturing process of semiconductor device comprising: a step performing fluorocarbon system plasma etch; a step performing slope etch by polymer attach process. Therefore, the present invention prevents the inside attachment or re-coating of silicide ion when a metal silicide layer is etched in a contact hole formation process for a semiconductor device.

Abstract translation: 目的：在半导体器件的接触孔形成工艺中，当蚀刻金属硅化物层时，提供半导体器件的制造工艺中的硅化物离子再涂覆防止方法，以防止硅化物离子的内部粘附或再涂覆。 构成：本发明公开了一种半导体器件的制造工艺中的硅化物离子重涂防止方法，包括：进行碳氟化合物系等离子体蚀刻的工序; 通过聚合物附着工艺执行斜坡蚀刻的步骤。 因此，本发明在用于半导体器件的接触孔形成工艺中蚀刻金属硅化物层时，防止硅化物离子的内部附着或再涂覆。

公开(公告)号：KR1019990025874A

公开(公告)日：1999-04-06

申请号：KR1019970047706

申请日：1997-09-19

Applicant: 삼성전자주식회사

Inventor： 전정식 ,  임훈 ,  안태혁

IPC: H01L21/76

Abstract: 본 발명은 피에스엘(PSL, Poly-Si Spacer LOCOS) 방법에 의한 반도체장치의 소자분리방법에 관한 것이다. 본 발명에 의한 반도체장치의 소자분리방법에 의하면 오아이에스에프(OISF, Oxidation Induced Stacking Fault)의 발생을 감소시켜 결함이 최소화된 활성영역을 확보할 수 있다. 따라서, 본 발명에 의하면 누설전류(leakage current)를 감소하여 반도체장치의 리프레쉬 (refresh)특성을 향상시킬 수 있다.

公开(公告)号：KR1019980068063A

公开(公告)日：1998-10-15

申请号：KR1019970004495

申请日：1997-02-14

Applicant: 삼성전자주식회사

Inventor： 전정식 ,  권상동 ,  정홍식 ,  민경진

IPC: H01L21/76

Abstract: 본 발명은 본 발명에 의한 반도체 소자의 트렌치 형성 방법을 개시한다. 이는 반도체 기판 상에 패드 산화막을 증착하는 제 1 단계; 상기 패드 산화막 상에 질화막(SiN)을 증착하여 물질층을 형성하는 제 2 단계; 상기 물질층 상에 감광막을 증착한 후 패터닝하는 제 3 단계; 상기 패터닝된 감광막을 마스크로하고 O
2 및 CHF
3 를 사용하여 상기 물질층과 패드 산화막을 식각하는 제 4 단계; 상기 감광막을 제거하는 제 5 단계; 및 상기 물질층을 마스크로하고 Cl
2 , HBr 및 O
2 를 사용하여 상기 반도체 기판을 식각하는 제 6 단계로 이루어진다. 즉, 고온 산화막/질화막 또는 질화막을 마스크층으로 이용하고 상기 마스크층과 그 하부의 패드 산화막을 동시에 식각함으로써 공정이 단순해지고, 상기 마스크층에 대한 반도체 기판의 식각 선택비가 큰 분위기에서 트렌치를 형성함으로써 상기 마스크층의 손상없이 일정한 선폭(critical dimension)의 트렌치를 형성할 수 있다는 잇점이 있다.