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公开(公告)号：KR1020060025262A
公开(公告)日：2006-03-21
申请号：KR1020040073629
申请日：2004-09-15
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115 , H01L21/28
CPC classification number: H01L21/31055 , H01L21/28273 , H01L27/11521
Abstract: 플래시 메모리 장치의 플로팅 게이트를 제조하는 방법에 있어서, 반도체 기판 상에 액티브 영역을 정의하며 상기 반도체 기판의 표면을 노출시키는 개구를 갖는 절연 패턴을 형성한다. 제1예비 폴리실리콘층은 상기 개구를 매립하도록 상기 절연 패턴 상에 형성된다. 상기 제1예비 폴리실리콘층을 형성하는 동안 상기 절연 패턴의 기하학적인 형상에 의해 상기 제1예비 폴리실리콘층 내에 생성된 보이드는 화학적 건식 식각 공정을 통해 제거된다. 상기 화학적 건식 식각 공정을 수행함으로써 상기 개구 내에 잔류하는 제1폴리실리콘층 및 상기 절연 패턴 상에 제2예비 폴리실리콘층을 형성한다. 상기 절연 패턴의 상부면이 노출되도록 상기 제2예비 폴리실리콘층의 상부를 제거하여 제1폴리실리콘층 및 제2폴리실리콘층을 포함하는 플로팅 게이트를 형성한다.
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公开(公告)号：KR1020040074348A
公开(公告)日：2004-08-25
申请号：KR1020030009917
申请日：2003-02-17
Applicant: 삼성전자주식회사
IPC: H01L21/762
CPC classification number: H01L51/0537 , H01L21/31051 , H01L21/316 , H01L21/31612 , H01L21/76224
Abstract: PURPOSE: A method for forming a thin film and a method for forming a trench isolation layer using the same are provided to reduce a defect of a SOG layer having an improved burying characteristic by performing only a soft baking process. CONSTITUTION: An SOG layer(34a) is formed by coating an SOG solution having polysilazane on the surface of a substrate(30) having a stepped part(32). The SOG layer is used for burying a recess formed by the stepped part. A soft baking process for the SOG layer is performed. An etch-back process for the SOG layer is performed. An insulating layer(36) is laminated on the substrate after the etch-back process for the SOG layer is performed.
Abstract translation: 目的：提供一种形成薄膜的方法和使用该方法形成沟槽隔离层的方法，通过仅进行软烘烤处理来减少具有改善的掩埋特性的SOG层的缺陷。 构成：通过在具有阶梯部（32）的基板（30）的表面上涂布具有聚硅氮烷的SOG溶液形成SOG层（34a）。 SOG层用于埋设由阶梯部形成的凹部。 进行SOG层的软烘烤处理。 执行用于SOG层的回蚀处理。 在执行SOG层的回蚀处理之后，在基板上层压绝缘层（36）。
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公开(公告)号：KR1020040050971A
公开(公告)日：2004-06-18
申请号：KR1020020078779
申请日：2002-12-11
Applicant: 삼성전자주식회사
IPC: H01L21/31
CPC classification number: H01L21/02164 , H01L21/02271 , H01L21/02304 , H01L21/31612 , H01L21/76224 , H01L21/76229
Abstract: PURPOSE: A gap fill method for manufacturing a semiconductor device is provided to be capable of filling an insulating layer in a gap region without voids or grooves. CONSTITUTION: A pattern having a gap region is formed on a semiconductor substrate(50). A lower oxide layer(62) is formed on the entire surface of the resultant structure for filling the gap region. An etch-back process is carried out on the lower oxide layer. At this time, the lower oxide layer exists at the lower portion of the gap region. An upper oxide layer(64) is selectively deposited on the lower oxide layer. Preferably, the pattern is completed by forming a hard mask pattern on the semiconductor substrate for partially exposing the semiconductor substrate and forming a trench region(54) in the semiconductor substrate using the hard mask pattern as an etching mask. Preferably, the upper oxide layer is formed by using O3 and TEOS(Tetra Ethyl Ortho Silicate) as source gas at the pressure of 200-760 torr and at the temperature of 300-560 °C.
Abstract translation: 目的：提供一种用于制造半导体器件的间隙填充方法，以能够在没有空隙或凹槽的间隙区域中填充绝缘层。 构成：在半导体衬底（50）上形成具有间隙区域的图案。 在所得结构的整个表面上形成下部氧化物层（62），用于填充间隙区域。 在低氧化物层上进行回蚀处理。 此时，低氧化物层存在于间隙区域的下部。 选择性地在低氧化物层上沉积上氧化物层（64）。 优选地，通过在半导体衬底上形成硬掩模图案以部分地暴露半导体衬底并且使用硬掩模图案作为蚀刻掩模在半导体衬底中形成沟槽区域（54）来完成图案。 优选地，通过使用O3和TEOS（四乙基原硅酸盐）作为源气体，在200-760乇的压力和在300-560℃的温度下形成上部氧化物层。
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公开(公告)号：KR100434187B1
公开(公告)日：2004-06-04
申请号：KR1020010049779
申请日：2001-08-18
Applicant: 삼성전자주식회사
IPC: H01L21/316
CPC classification number: H01L21/76897 , H01L21/31051 , H01L21/76819 , H01L21/76828 , H01L21/76834 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/935 , H01L2924/00
Abstract: Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device. Thus, a planar silicon oxide layer is formed between conductive patterns having a fine interval therebetween without creating a void. In addition, a metal layer pattern, which acts as a conductor in the conductive patterns, can be prevented from being oxidized when the silicon oxide layer is formed.
Abstract translation: 公开了一种用于形成半导体器件的氧化硅层的方法，所述半导体器件能够在精细导电图案之间绝缘而不会导致工艺失败，并且用于形成具有氧化硅层的布线。 在半导体衬底上形成导电图案之后，在导电图案上和半导体衬底上依次形成抗氧化层。 抗氧化层防止氧化剂渗透到导电图案和半导体衬底中。 通过在埋入导电图案的同时在抗氧化层上涂覆可回流氧化材料来形成可回流氧化物层。 氧化硅层通过对可回流氧化物层进行热处理而形成。 然后，对导体图案和暴露于半导体基板的抗氧化层之间填充的氧化硅层进行蚀刻，以形成接触孔，由此形成半导体器件的布线。 因此，在具有精细间隔的导电图案之间形成平面氧化硅层而不会产生空隙。 此外，当形成氧化硅层时，可以防止用作导电图案中的导体的金属层图案被氧化。
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公开(公告)号：KR1020030015931A
公开(公告)日：2003-02-26
申请号：KR1020010049779
申请日：2001-08-18
Applicant: 삼성전자주식회사
IPC: H01L21/316
CPC classification number: H01L21/76897 , H01L21/31051 , H01L21/76819 , H01L21/76828 , H01L21/76834 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/935 , H01L2924/00
Abstract: PURPOSE: A method for forming a silicon oxide layer of a semiconductor device and a method for forming a wire having a silicon oxide layer are provided to insulate patterns without forming a void between the patterns arrayed according to a fine interval. CONSTITUTION: A plurality of conductive patterns(32) are formed on a semiconductor substrate(30). The conductive patterns(32) are formed with a metal layer pattern(32a) and a nitride layer pattern(32b). The metal layer pattern(32a) is used as a conductor. A protective oxide layer is formed on the conductive patterns(32) and the semiconductor substrate(30). A floating oxide layer is formed by coating a floating oxide on the conductive patterns(32) having the protective oxide layer. A silicon oxide layer(40) is formed by performing a thermal process for the floating oxide layer.
Abstract translation: 目的：提供一种用于形成半导体器件的氧化硅层的方法和用于形成具有氧化硅层的布线的方法，以在不形成根据细微间隔排列的图案之间的空隙的情况下绝缘图案。 构成：在半导体衬底（30）上形成多个导电图案（32）。 导电图案（32）由金属层图案（32a）和氮化物层图案（32b）形成。 金属层图案（32a）用作导体。 在导电图案（32）和半导体衬底（30）上形成保护氧化层。 通过在具有保护氧化物层的导电图案（32）上涂覆浮动氧化物来形成浮动氧化物层。 通过对浮动氧化物层进行热处理形成氧化硅层（40）。
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Patent Agency Ranking
公开(公告)号：KR100354442B1
公开(公告)日：2002-09-28
申请号：KR1020000075179
申请日：2000-12-11
Applicant: 삼성전자주식회사
IPC: H01L21/316
Abstract: 본 발명은 반도체 장치의 SOG막 절연막 형성 방법에 관한 것으로, 본 발명의 방법은, 복수의 단차진 패턴을 가지는 기판에 폴리실라제인을 이용하여 SOG 절연막을 도포하고, 상기 절연막의 용매성분을 제거하기 위한 50 내지 350℃ 온도 범위의 프리 베이크와, 파티클 생성 억제를 위한 350 내지 500℃ 온도 범위의 하드 베이크와, 600 내지 1200℃ 온도 범위의 바람직하게는 700 내지 900℃ 온도 범위의 어닐링을 실시하는 단계를 구비하는 것을 특징으로 한다. 하드 베이크를 하지 않고, 혹은 하드 베이크와 어닐링 사이에 CMP를 통한 평탄화 단계가 더 구비되거나 될 수 있다.
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公开(公告)号：KR1020020045783A
公开(公告)日：2002-06-20
申请号：KR1020000075179
申请日：2000-12-11
Applicant: 삼성전자주식회사
IPC: H01L21/316
CPC classification number: H01L21/02282 , H01L21/02123 , H01L21/02222 , H01L21/02337 , H01L21/316 , H01L21/76819 , H01L21/76828 , H01L21/76837
Abstract: PURPOSE: A method for fabricating a spin-on-glass(SOG) insulation layer of a semiconductor device is provided to control particles caused by gas generated from the SOG layer and to prevent a crack on the SOG layer after a high temperature annealing process, by using the SOG layer in a portion where patterns are dense. CONSTITUTION: The SOG insulation layer(55'') is applied on a substrate(51) having a plurality of stepped patterns by using poly silazane of a solution state. A pre-bake process is performed within a temperature range of 50-350 deg.C to eliminate a solvent component of the insulation layer. A hard bake process is performed within a temperature range of 350-500 deg.C. An annealing process is performed within a temperature scope of 600-1200 deg.C.
Abstract translation: 目的：提供一种用于制造半导体器件的旋涂玻璃（SOG）绝缘层的方法，以控制由SOG层产生的气体引起的颗粒，并且在高温退火处理之后防止SOG层上的裂纹， 通过在图案密集的部分中使用SOG层。 构成：通过使用溶液状态的聚硅氮烷，将SOG绝缘层（55“）施加在具有多个阶梯状图案的基板（51）上。 在50-350摄氏度的温度范围内进行预烘烤处理，以消除绝缘层的溶剂成分。 硬烘烤过程在350-500摄氏度的温度范围内进行。 在600-1200℃的温度范围内进行退火处理。
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公开(公告)号：KR1020020009882A
公开(公告)日：2002-02-02
申请号：KR1020000043427
申请日：2000-07-27
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: PURPOSE: A shallow trench isolation method of a semiconductor integrated circuit is provided to prevent a short-circuit phenomenon of a gate and to prevent over-recess of an isolation layer caused by incomplete densification in a trench region, by filling the trench region with a spin-on-glass(SOG) layer and by performing a heat treatment for densification after a chemical mechanical polishing(CMP) process. CONSTITUTION: A trench etch stop layer pattern exposing a predetermined region of a semiconductor substrate(10) is formed on the semiconductor substrate. The exposed semiconductor substrate is etched to form the trench region(18) confining an active region. The resultant structure having the trench region is thermally oxidized to form a thermal oxide layer(20). The SOG layer filling the trench region is formed on the resultant structure having the thermal oxide layer. The SOG layer is planarized to form the isolation layer(24a) inside the trench region. A heat treatment process is performed regarding the resultant structure having the isolation layer.
Abstract translation: 目的：提供半导体集成电路的浅沟槽隔离方法，以防止栅极的短路现象，并且通过在沟槽区域中填充沟槽区域来防止由沟槽区域中不完全致密化引起的隔离层的过度凹陷 旋涂玻璃（SOG）层，并进行化学机械抛光（CMP）工艺后的致密化热处理。 构成：在半导体衬底上形成露出半导体衬底（10）的预定区域的沟槽蚀刻停止层图案。 蚀刻暴露的半导体衬底以形成限制有源区的沟槽区（18）。 具有沟槽区域的所得结构被热氧化以形成热氧化物层（20）。 在具有热氧化物层的所得结构上形成填充沟槽区域的SOG层。 SOG层被平坦化以在沟槽区域内形成隔离层（24a）。 对具有隔离层的结构进行热处理。
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公开(公告)号：KR101767664B1
公开(公告)日：2017-08-11
申请号：KR1020110029043
申请日：2011-03-30
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76229 , H01L27/1052 , H01L27/10894 , H01L27/11531 , H01L29/945
Abstract: 반도체소자의제조방법이제공된다. 상기반도체소자의제조방법은, 제1 및제2 영역들을포함하는기판을준비하는것, 상기제1 및제2 영역들내에, 제1 폭을갖는제1 트렌치및 상기제1 폭보다넓은제2 폭을제2 트렌치를각각형성하는것, 상기제1 및제2 트렌치들내에제1 절연막을형성하는것, 상기제2 트렌치내의상기제1 절연막을제거하고, 상기제1 트렌치내에상기제1 절연막의일부분을잔존시켜, 상기제1 트렌치내에제1 절연패턴을형성하는것, 및상기기판상에, 상기제2 트렌치를채우고, 상기제1 절연막과다른물질을포함하는제2 절연막을형성하는것을포함한다.
Abstract translation: 提供了一种制造半导体器件的方法。 1.一种制造半导体器件的方法，包括：准备包括第一和第二区域的衬底;在第一和第二区域中形成具有第一宽度和大于第一宽度的第二宽度的第一沟槽 在第一和第二沟槽中形成第一绝缘膜;去除第二沟槽中的第一绝缘膜并在第一沟槽中留下第一绝缘膜的一部分; 在第一沟槽中形成第一绝缘图案，并且将第二沟槽填充在衬底上;以及形成包括与第一绝缘膜不同的材料的第二绝缘膜。
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公开(公告)号：KR101609251B1
公开(公告)日：2016-04-05
申请号：KR1020090074878
申请日：2009-08-13
Applicant: 삼성전자주식회사
IPC: H01L21/306
CPC classification number: H01L28/91 , H01L21/31111 , H01L27/10817 , H01L27/10852
Abstract: 본발명은반도체미세구조물의제조방법에관한것으로서, 더욱구체적으로는반도체기판위에 III족질화물의하부물질층을형성하는단계; 상기하부물질층위에몰드물질층을형성하는단계; 상기몰드물질층위에, 상기몰드물질층내에구조물을형성하기위한식각마스크층을형성하는단계; 상기식각마스크층을마스크로서이용하여상기몰드물질층및 상기하부물질층을이방성식각하는단계; 및상기몰드물질층및 상기하부물질층을등방성식각하는단계를포함하는반도체미세구조물의제조방법을제공한다. 본발명의반도체미세구조물의제조방법을이용하면식각저지막과같은하부물질층이있는경우다양한구조의반도체미세구조물을희망하는바에따라용이하게얻을수 있는효과가있다.
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