公开(公告)号：KR1020120110878A

公开(公告)日：2012-10-10

申请号：KR1020110029043

申请日：2011-03-30

Applicant: 삼성전자주식회사

Inventor： 변경문 ,  최병덕 ,  홍은기 ,  강만석

IPC: H01L21/76

CPC classification number: H01L21/76229 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11531 ,  H01L29/945

Abstract: PURPOSE: A semiconductor device for high integration and a manufacturing method thereof are provided to have high reliability by preventing the recess of a first element isolation pattern including a first insulating pattern made of nitride. CONSTITUTION: A first insulating pattern(132) is made of silicon nitride. A second liner pattern(124) covers a sidewall and a bottom surface of a second trench(114). The second liner pattern is made of same material as a first liner pattern. A second insulating pattern(144) is contacted to the second liner pattern. The second insulating pattern is made of different material as the first insulating pattern.

Abstract translation: 目的：提供一种用于高集成度的半导体器件及其制造方法，通过防止包含由氮化物构成的第一绝缘图案的第一元件隔离图案的凹部而具有高可靠性。 构成：第一绝缘图案（132）由氮化硅制成。 第二衬垫图案（124）覆盖第二沟槽（114）的侧壁和底表面。 第二衬里图案由与第一衬里图案相同的材料制成。 第二绝缘图案（144）与第二衬垫图案接触。 第二绝缘图案由不同的材料制成作为第一绝缘图案。

公开(公告)号：KR1020080029151A

公开(公告)日：2008-04-03

申请号：KR1020060094788

申请日：2006-09-28

Applicant: 삼성전자주식회사

Inventor： 라상호 ,  김성태 ,  백은경 ,  구주선 ,  변경문

IPC: H01L21/31

CPC classification number: H01L21/32105 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/324

Abstract: A method for forming an insulating layer of a semiconductor device is provided to improve the gap filling of an insulating layer by improving surface roughness in a gap-fill part. A structure(108) is formed on a semiconductor substrate(100). A surface pre-treatment process is performed to remove the semiconductor substrate and a part of an upper surface of the structure. An SOG layer coating process is performed to form an SOG layer by coating an SOG material to bury the pre-treated structure. A silicon oxide layer is formed by heat-treating the SOG layer. The SOG material includes an SOG solution which is formed by resolving the polisilazane in an organic solvent. The pre-treatment process includes an etch process or a plasma process using a wet-etch solution.

Abstract translation: 提供一种用于形成半导体器件的绝缘层的方法，以通过改善间隙填充部分中的表面粗糙度来改善绝缘层的间隙填充。 在半导体衬底（100）上形成结构（108）。 执行表面预处理工艺以去除半导体衬底和结构的上表面的一部分。 通过涂覆SOG材料以掩埋预处理的结构，进行SOG层涂覆工艺以形成SOG层。 通过对SOG层进行热处理形成氧化硅层。 SOG材料包括通过在有机溶剂中拆分聚苯并咪唑而形成的SOG溶液。 预处理工艺包括使用湿蚀刻溶液的蚀刻工艺或等离子体工艺。

公开(公告)号：KR101284146B1

公开(公告)日：2013-07-10

申请号：KR1020070072458

申请日：2007-07-19

Applicant: 삼성전자주식회사

Inventor： 변경문 ,  구주선 ,  라상호 ,  백은경 ,  최종완

IPC: H01L21/76

CPC classification number: H01L21/76229

Abstract: 트렌치 소자분리 영역을 갖는 반도체소자 및 그 제조방법을 제공한다. 이 방법은 기판에 제1 트렌치 영역 및 상기 제1 트렌치 영역보다 큰 폭을 갖는 제2 트렌치 영역을 형성하는 것을 포함한다. 상기 제1 및 제2 트렌치 영역들을 채우는 하부 물질막을 형성한다. 제1 식각공정을 이용하여 상기 하부 물질막을 식각하여 상기 제1 트렌치 영역에 잔존하는 제1 예비 하부 물질 패턴 및 상기 제2 트렌치 영역에 잔존하며 상기 제1 예비 하부 물질 패턴과 다른 레벨에 위치하는 상부면을 갖는 제2 예비 하부 물질 패턴을 형성한다. 제2 식각 공정을 이용하여 상기 제1 및 제2 예비 하부 물질패턴들을 식각하여 실질적으로 동일한 레벨에 위치하는 상부면을 갖는 제1 및 제2 하부 물질 패턴들을 형성한다. 상기 제1 하부 물질 패턴 상에 제1 상부 물질 패턴을 형성함과 아울러 상기 제2 하부 물질 패턴 상에 제2 상부 물질 패턴을 형성한다.

公开(公告)号：KR1020120023326A

公开(公告)日：2012-03-13

申请号：KR1020100086174

申请日：2010-09-02

Applicant: 삼성전자주식회사

Inventor： 오경석 ,  변경문 ,  김신혜 ,  정덕영 ,  최길현 ,  홍은기

IPC: C09K3/00 ,  H01L21/027

CPC classification number: H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/76224 ,  C09K3/00 ,  H01L21/0274

Abstract: PURPOSE: An oxidation accelerator composition is provided to obtain denser oxide membrane with high yield even at low temperature. CONSTITUTION: An oxidation accelerator composition comprises an oxidation promoter having the structure of chemical formula 1: A-M-L, and solvent capable of dissolving the oxidation promoter. The concentration of the oxidation promoter is 1×10^(-6) - 1×10^(-2) M. In chemical formula 1, L is a silicon, silicon oxide, silicon nitride, or a functional group capable of chemically absorbing to metal surface, A is a functional group having oxidation ability, and M is a moiety which connects the A and the L by covalent bonding, and capable of being heat-decomposed.

Abstract translation: 目的：提供氧化促进剂组合物，即使在低温下也能以高产率获得更密集的氧化膜。 构成：氧化促进剂组合物包含具有化学式1：A-M-L结构的氧化促进剂和能够溶解氧化促进剂的溶剂。 氧化促进剂的浓度为1×10 ^（ - 6） - 1×10 ^（ - 2）M。在化学式1中，L为硅，氧化硅，氮化硅或能够化学吸收的官能团 金属表面，A是具有氧化能力的官能团，M是通过共价键连接A和L并能够被热分解的部分。

公开(公告)号：KR1020080010823A

公开(公告)日：2008-01-31

申请号：KR1020060071388

申请日：2006-07-28

Applicant: 삼성전자주식회사

Inventor： 변경문 ,  차용원 ,  이보영 ,  서동철

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/02274 ,  H01L21/76837

Abstract: An interconnection structure having an air-gap in a semiconductor device and a method of manufacturing the same are provided to remove a pointed portion of an insulating structure confining the air-gap at the time of forming the air-gap between the interconnection structures, thereby simultaneously improving mechanical and electrical characteristics. An interconnection structure having an air-gap in a semiconductor device includes conductive film patterns(110) and an insulating structure(150). The conductive film patterns have a plurality of lines. The conductive film patterns are buried in the insulating structure. The air-gap having a rounded upper portion is formed in the insulating structure of a part positioned between the conductive film patterns. The conductive film patterns are formed on a semiconductor substrate(100) such as a silicon wafer or an SOI(Silicon On Insulator). An interlayer insulating film having a flat top surface is interposed between the semiconductor substrate and the conductive film patterns. Opening portions(115) are formed between the conductive film patterns adjacent to each other at a predetermined interval.

Abstract translation: 提供了一种在半导体器件中具有气隙的互连结构及其制造方法，以在形成互连结构之间的气隙时去除限制空隙的绝缘结构的尖端部分，由此 同时提高机械和电气特性。 在半导体器件中具有气隙的互连结构包括导电膜图案（110）和绝缘结构（150）。 导电膜图案具有多条线。 导电膜图案埋在绝缘结构中。 具有圆形上部的气隙形成在位于导电膜图案之间的部分的绝缘结构中。 导电膜图案形成在诸如硅晶片或SOI（绝缘体上硅）的半导体衬底（100）上。 在半导体衬底和导电膜图案之间插入具有平坦顶表面的层间绝缘膜。 在预定间隔彼此相邻的导电膜图案之间形成开口部（115）。

公开(公告)号：KR101616045B1

公开(公告)日：2016-04-28

申请号：KR1020090112188

申请日：2009-11-19

Applicant: 삼성전자주식회사

Inventor： 김신혜 ,  변경문 ,  김홍래 ,  최길현 ,  홍은기

IPC: H01L21/8242

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/91

Abstract: 본발명의사상은 OCS 구조의커패시터를포함한반도체소자에있어서, 셀에지(cell edge) 부분에서발생하는커패시터쓰러짐또는뜯김현상을방지할수 있는반도체소자, 그반도체소자를포함한전기전자장치, 및그 반도체소자형성방법을제공한다. 그반도체소자제조방법은셀 영역이정의된반도체기판전면으로몰드산화막(mold oxide layer)을형성하는단계; 상기몰드산화막상에인장응력이소정값보다높고습식식각에내성이강한재질로지지대막을형성하는단계; 상기몰드산화막및 지지대막을식각하여, 상기반도체기판상에형성된도전층을노출시키는복수개의홀을형성하는단계; 상기홀 내벽으로도전성물질을도포하여복수개의실린더형하부전극을형성하는단계; 상기지지대막을소정패턴으로식각하여, 띠(stripe) 형태를가지고인접하는상기하부전극들사이를연결하는복수개의커패시터지지대를형성하는단계; 및상기하부전극상으로유전체막및 상부전극을형성하는단계;를포함한다.

公开(公告)号：KR1020140146705A

公开(公告)日：2014-12-29

申请号：KR1020130069032

申请日：2013-06-17

Applicant: 삼성전자주식회사

Inventor： 김홍래 ,  최병덕 ,  박희영 ,  노상호 ,  박진형 ,  변경문

IPC: H01L27/108 ,  H01L21/8242 ,  H01L21/31

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

Abstract: A semiconductor device is provided. The semiconductor device includes first and second wire structures which are arranged on a substrate. Insulation separation patterns are arranged between the first and second wire structures. A conductive structure is arranged between the first and second wire structures and between the insulation separation patterns. A first empty space which includes a first part between the first wire structure and the conductive structure and a second part between the first wire structure and the insulation separation patterns is arranged. A second empty space which includes a first part between the second wire structure and the conductive structure and a second part between the second wire structure and the insulation separation patterns is arranged. The height of the first part of the first empty space is different from the height of the second part of the first empty space.

Abstract translation: 提供半导体器件。 半导体器件包括布置在衬底上的第一和第二线结构。 绝缘分离图案布置在第一和第二线结构之间。 导电结构布置在第一和第二线结构之间以及绝缘分离图案之间。 布置有包括第一线结构和导电结构之间的第一部分和第一线结构和绝缘分离图案之间的第二部分的第一空白空间。 布置了第二空白空间，其包括在第二线结构和导电结构之间的第一部分和在第二线结构和绝缘分离图案之间的第二部分。 第一空白空间的第一部分的高度与第一空白空间的第二部分的高度不同。

公开(公告)号：KR1020120098127A

公开(公告)日：2012-09-05

申请号：KR1020110017872

申请日：2011-02-28

Applicant: 삼성전자주식회사

Inventor： 변경문 ,  김형수 ,  홍은기 ,  강만석

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10808 ,  H01L27/10852 ,  H01L28/90

Abstract: PURPOSE: A semiconductor memory device and a forming method thereof are provided to optimize a pattern by including a first sub pattern and a second sub pattern in a support pattern. CONSTITUTION: A storage node(155) and an electrode film(170) are arranged on a substrate(100). A capacitor dielectric is arranged between the storage node and the electrode film. A supporter pattern(130a) is arranged on one side of the storage node and includes a first sub pattern and a second sub pattern. The first sub pattern includes materials with an etch selectivity with regard to the second sub pattern.

Abstract translation: 目的：提供一种半导体存储器件及其形成方法，用于通过在支持图案中包括第一子图案和第二子图案来优化图案。 构成：存储节点（155）和电极膜（170）布置在基板（100）上。 在存储节点和电极膜之间布置有电容器电介质。 支撑图案（130a）布置在存储节点的一侧，并且包括第一子图案和第二子图案。 第一子图案包括关于第二子图案具有蚀刻选择性的材料。

公开(公告)号：KR1020100090397A

公开(公告)日：2010-08-16

申请号：KR1020090009641

申请日：2009-02-06

Applicant: 삼성전자주식회사

Inventor： 변경문 ,  정덕영 ,  구주선 ,  홍은기

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837

Abstract: PURPOSE: A method for forming a semiconductor device is provided to improve the quality of the semiconductor device by preventing a recess from being formed on an insulating film. CONSTITUTION: A recess region is defined on a semiconductor substrate(110). A silicon oxide film(120) is formed in the recess region. The surface of the silicon oxide film is treated using a nitride catalyst in order to form a nitride resultant(124) on the surface of the silicon oxide film. An insulating film is formed on the silicon oxide film with the nitride resultant. The insulating film is thermally treated.

Abstract translation: 目的：提供一种用于形成半导体器件的方法，以通过防止在绝缘膜上形成凹陷来改善半导体器件的质量。 构成：在半导体衬底（110）上限定凹陷区域。 在凹陷区域中形成氧化硅膜（120）。 使用氮化物催化剂处理氧化硅膜的表面，以在氧化硅膜的表面上形成氮化物结合物（124）。 在氧化硅膜上形成有氮化物结晶的绝缘膜。 对绝缘膜进行热处理。

公开(公告)号：KR1020170123377A

公开(公告)日：2017-11-08

申请号：KR1020160052145

申请日：2016-04-28

Applicant: 삼성전자주식회사

Inventor： 변경문 ,  도신해 ,  임바드로

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/3213 ,  G03F1/46 ,  G03F7/20 ,  H01L21/02

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/28017 ,  H01L21/32139

Abstract: 본발명의실시예에따른반도체소자의패턴형성방법을제공한다. 반도체소자의패턴형성방법은셀 영역과주변회로영역을가지는기판상에하드마스크막, 희생막및 반사방지막을순차적으로형성하고, 상기희생막을패터닝하여상기셀 영역상의제 1 희생패턴및 상기주변회로영역상의제 2 희생패턴을형성하고, 상기제 1 희생패턴및 상기제 2 희생패턴의측벽들을덮는스페이서들을형성하고, 그리고, 상기제 1 희생패턴을제거하는것을포함한다. 상기반사방지막은서로다른물질로형성되고상기희생막상에순차적으로적층되는하부반사방지막및 상부반사방지막을포함한다.

Abstract translation: 提供了根据本发明实施例的形成半导体器件的图案的方法。 的半导体装置的图案形成方法是第一牺牲图案和所述外围单元区域上，以形成硬掩模层，所述牺牲层和防反射膜顺次具有单元区域和外围电路区域的基板上的，图案化牺牲薄膜电路 在所述区域上的第二牺牲图案，以及在所述第一牺牲图案和覆盖第二牺牲图案的侧壁间隔件，然后包括去除所述第一牺牲图案。 抗反射膜包括下抗反射膜和由不同材料形成的上抗反射膜，并顺序堆叠在牺牲膜上。