Abstract:
에피택셜 그래핀(epitaxial graphene)을 포함하는 적층구조물, 상기 적층구조물의 형성방법 및 상기 적층구조물을 포함하는 전자 소자에 대해 개시되어 있다. 개시된 본 발명의 적층구조물은 본 발명의 일 실시예는 Si 기판, 상기 Si 기판 상에 구비된 하지층, 및 상기 하지층 상에 구비된 적어도 한 층의 에피택셜 그래핀(epitaxial graphene)을 포함하는 적층구조물을 제공한다.
Abstract:
앰비폴라 물질을 이용한 전계효과 트랜지스터 및 논리회로를 개시한다. 개시된 앰비폴라 물질을 이용한 전계효과 트랜지스터는: 소스 영역 및 드레인 영역과, 그 사이의 채널 영역을 포함하며 상기 소스 영역, 드레인 영역 및 채널 영역이 일체형으로 형성된 앰비폴라층; 상기 채널 영역에 형성된 게이트 전극; 및 상기 앰비폴라층으로부터 상기 게이트 전극을 이격시키는 절연층;을 구비한다. 상기 소스 영역으로부터 상기 드레인 영역으로의 제1방향과 직교하는 제2방향에서 상기 소스 영역 및 드레인 영역의 폭이 상기 채널 영역보다 더 넓게 형성된다.
Abstract:
Disclosed are a graphene memory using a graphene layer as a charge-trap layer and a method of operating the same. The graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate; a graphene layer which comes into contact with the conductive semiconductor substrate and is spaced apart from the source and the drain on the substrate between the source and the drain; and a gate electrode formed on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer stores charges.
Abstract:
An electronic device is disclosed. The disclosed electronic device includes a semiconductor layer, graphene which is directly in contact with the preset region of the semiconductor layer, and a metal layer which is formed on the graphene. The semiconductor layer has a totally uniform doping concentration or has a preset region of a doping concentration of 10^19 cm^-3 or less.
Abstract:
Disclosed is a tunneling field effect transistor including a graphene channel. The disclosed tunneling field effect transistor comprises a first electrode on a substrate, a semiconductor layer on the first electrode, a graphene channel which is extended in a first region which is separated from the first electrode on the semiconductor layer, a second electrode on the graphene channel disposed on the first region, a gate insulating layer which covers the graphene channel, and a gate electrode on the gate insulating layer. The first electrode and the graphene channel face the semiconductor layer in the second region.
Abstract:
PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve applicability of a high speed operation element by forming an inter layer dielectric and a gate insulating layer by using different material. CONSTITUTION: A gate electrode(12) is formed on a substrate(10). The gate electrode comprises a projected gate finger. A gate insulating layer(13) is formed on the gate electrode. An inter-layer insulating film(11) is formed on the side of the gate insulating layer and the gate electrode. The inter-layer insulating film comprises a material having dielectric permittivity lower than the gate insulating layer. A graphene layer(14) is formed on the gate insulating layer and the inter-layer insulating film. A source(15a) and a drain(15b) are formed on the graphene layer. Graphene is formed in the lower side of the graphene layer between the source and drain.
Abstract:
PURPOSE: Graphene, a method for manufacturing the same, and a transistor including the same are provided to substitute boron and nitrogen in the graphene at the same ratio using borazine or ammonia borane as a precursor. CONSTITUTION: Band gap is formed in graphene by substituting a part of carbon atoms with boron and nitrogen. 1-20% of the carbon atoms in the graphene are substituted. The density difference of the boron and the nitrogen is 1013cm^-2 or less. When the graphene is formed through a chemical vapor deposition method, borazine or ammonia borane is used as the precursor of the boron and the nitrogen.