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公开(公告)号：KR1020110085339A
公开(公告)日：2011-07-27
申请号：KR1020100005077
申请日：2010-01-20
Applicant: 포항공과대학교 산학협력단
CPC classification number: H03F1/3247 , H03F1/3276 , H03F3/24 , H03F2201/3224
Abstract: PURPOSE: A pre-distortion system for compensating for a memory effect of a power amplifier and a method thereof are provided to adjust a collector bias voltage of a transistor configuring a distortion generator, thereby easily adjusting the amplitude of a distortion signal. CONSTITUTION: A first power distributor(401) distributes the first and second signals inputted to a power amplifier. A plurality of distortion generators receives and distributes the second signals. A second path unit(403) generates a plurality of distortion signals with different delay using the distortion generators. A first path unit(402) receives the first signals and delays the first signals as much as the delay of the second path unit. A first power coupler(404) couples outputs of the first and second path units.
Abstract translation: 目的：提供用于补偿功率放大器的存储器效应的预失真系统及其方法，以调整构成失真发生器的晶体管的集电极偏置电压，从而容易地调整失真信号的幅度。 构成：第一分配器（401）分配输入到功率放大器的第一和第二信号。 多个失真发生器接收和分配第二信号。 第二路径单元（403）使用失真发生器产生具有不同延迟的多个失真信号。 第一路径单元（402）接收第一信号并将第一信号延迟第二路径单元的延迟。 第一功率耦合器（404）耦合第一和第二路径单元的输出。
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公开(公告)号：KR100853166B1
公开(公告)日：2008-08-20
申请号：KR1020070009217
申请日：2007-01-30
Applicant: 포항공과대학교 산학협력단
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/7783 , H01L21/28587 , H01L29/42316 , H01L29/66462
Abstract: 본 발명은 화화물 반도체를 기반으로 하는 전계효과형 메타모픽(metamorphic) 고전자 이동도 트랜지스터(HEMT : high electron mobility transistor)를 제작하는 방법에 있어, T-게이트를 기판상에 안정적으로 형성하는 방법에 관한 것으로서 기판 위에 복수의 레지스트를 순차적으로 적층하는 단계; 상기 적층된 레지스트에 전자빔 리소그래피를 이용하여 T형 패턴을 형성하는 단계; 상기 T형 패턴이 형성된 기판 위에 게이트 금속층을 형성하는 단계; 접착부재를 상기 적층된 레지스트의 최상층에 형성된 게이트 금속층과 접착되도록 한 후 상기 접착부재를 분리시킴으로써 상기 게이트 금속층을 제거하는 단계; 및 상기 적층된 레지스트를 모두 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다. 또한 기판 위에 복수의 에피텍셜층이 형성된 화합물 반도체에 있어서, 캡층의 하부에 형성된 식각방지층을 고농도로 도핑함으로써 반도체 소자의 기생 저항을 줄이는 것을 또 다른 특징으로 한다. 본 발명에 따르면 접착 부재를 이용한 금속 제거 기법을 이용하여 안정적으로 미세 게이트를 형성할 수 있으며, 고농도 도핑된 인듐인 식각 방지층을 도입한 에피 구조를 이용하여 기생 저항 성분을 줄임으로써 초고속 동작이 가능한 고전자 이동도 트랜지스터 제조 기법을 제공한다.
화합물 반도체, 고전자 이동도 트랜지스터, 접착 부재, 금속 제거 기법-
公开(公告)号：KR100795242B1
公开(公告)日：2008-01-15
申请号：KR1020060108497
申请日：2006-11-03
Applicant: 학교법인 포항공과대학교 , 포항공과대학교 산학협력단
IPC: H01L21/336 , H01L21/027
CPC classification number: H01L29/7787 , H01L29/42316 , H01L29/66462 , H01L21/28114 , G03F7/2059 , H01J37/3174
Abstract: A method for forming a gate of a semiconductor device and the gate structure are provided to generate a stable schottky junction on a T-gate by stably supporting a wide gate head using a curved gate support. A gate of a semiconductor device includes a wide gate head(402) and a narrow gate support(404). First to third resists with different electron beam intensities are applied on a semiconductor substrate. A first exposure process is performed on the semiconductor substrate using the electron beam, and the third resist is selectively developed. The second resist is selectively developed on a region wider than the third resist, such that a gate head region is defined. A second exposure process is performed on the semiconductor substrate, on which the third and second resists are selectively developed, and the first resist is selectively developed at a low temperature. A metal is deposited on the first to third resists, and the first to third resists are removed.
Abstract translation: 提供一种用于形成半导体器件的栅极和栅极结构的方法，以通过使用弯曲栅极支撑件稳定地支撑宽栅极头，在T栅极上产生稳定的肖特基结。 半导体器件的栅极包括宽栅极头（402）和窄栅极支撑（404）。 在半导体衬底上施加具有不同电子束强度的第一至第三抗蚀剂。 使用电子束在半导体基板上进行第一曝光处理，并且选择性地显影第三抗蚀剂。 第二抗蚀剂在比第三抗蚀剂宽的区域选择性地显影，从而限定了栅极头区域。 在其上选择性地显影第三和第二抗蚀剂的半导体衬底上进行第二曝光处理，并且在低温下选择性地显影第一抗蚀剂。 金属沉积在第一至第三抗蚀剂上，并且第一至第三抗蚀剂被去除。
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公开(公告)号：KR101805247B1
公开(公告)日：2018-01-10
申请号：KR1020150010432
申请日：2015-01-22
Applicant: 포항공과대학교 산학협력단
Abstract: 입력벡터를통해인가되는패턴화된이미지정보를분류할수 있는신경회로망형태분류기및 이를이용하는형태분류방법이개시된다. 패턴을인식하기위해구비되는뉴런부에는금속-절연체전이소자가사용된다. 인식하고자하는패턴이인가되는경우, 금속-절연체전이소자는발진동작을통해출력신호의변동을유발한다. 또한, 인식하고자하는패턴에서벗어나는경우, 금속 -절연체전이소자는고저항상태를유지하여일정한레벨로수렴하는출력신호를생성한다. 이를통해패턴을용이하게인식할수 있다.
Abstract translation: 一种能够对通过输入矢量应用的图案化图像信息进行分类的神经网络类型分类器以及使用该分类器的形态分类方法。 在提供用于识别图案的神经元部分中使用金属 - 绝缘体过渡元件。 当应用待识别的图案时，金属 - 绝缘体转变元件通过振荡操作引起输出信号的波动。 另外，当图案偏离要被识别的图案时，金属 - 绝缘体转变装置保持高电阻状态并且产生会聚在恒定电平的输出信号。 这使得识别图案变得容易。
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Patent Agency Ranking
公开(公告)号：KR1020130120969A
公开(公告)日：2013-11-05
申请号：KR1020120084943
申请日：2012-08-02
Applicant: 삼성전자주식회사 , 포항공과대학교 산학협력단
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/42392 , H01L29/1033
Abstract: Provided is a field effect transistor which includes a drain region, a source region, and a channel region. Provided are a gate electrode which surrounds a part of the channel region and a gate insulation layer which is located between the channel region and the gate electrode. The cross section of the channel region in contact with the source region is smaller than the cross section of the channel region in contact with the drain region.
Abstract translation: 提供了包括漏极区域，源极区域和沟道区域的场效应晶体管。 提供围绕沟道区的一部分的栅电极和位于沟道区和栅电极之间的栅极绝缘层。 与源极区域接触的沟道区域的截面小于与漏极区域接触的沟道区域的截面。
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公开(公告)号：KR1020130020458A
公开(公告)日：2013-02-27
申请号：KR1020110083105
申请日：2011-08-19
Applicant: 포항공과대학교 산학협력단
CPC classification number: H01L31/035227 , H01L31/022466 , H01L31/02327 , H01L31/035281 , H01L31/0547 , H01L31/068 , H01L31/18 , Y02E10/52 , Y02E10/547
Abstract: PURPOSE: A solar cell and a manufacturing method thereof are provided to improve photoelectric conversion efficiency by forming each tilt sidewall of a plurality of silicon nanowires. CONSTITUTION: A rear electrode(600) is formed on one side of a substrate. A p-type semiconductor layer includes a plurality of nanowires which are vertically arranged on the rear of the substrate. An n-type semiconductor layer(300) is formed on the p-type semiconductor along the surface of the plurality of nanowires. A front electrode(500) is formed on the n-type semiconductor layer. An insulation layer(700) covers the front electrode and the n-type semiconductor layer and fills a space between the plurality of nanowires.
Abstract translation: 目的：提供太阳能电池及其制造方法，以通过形成多个硅纳米线的每个倾斜侧壁来提高光电转换效率。 构成：背面电极（600）形成在基板的一侧。 p型半导体层包括垂直布置在基板的后部的多个纳米线。 沿着多个纳米线的表面在p型半导体上形成n型半导体层（300）。 在n型半导体层上形成有前电极（500）。 绝缘层（700）覆盖前电极和n型半导体层，并填充多个纳米线之间的空间。
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公开(公告)号：KR1020120117231A
公开(公告)日：2012-10-24
申请号：KR1020110034860
申请日：2011-04-14
Applicant: 포항공과대학교 산학협력단
IPC: G01N27/30 , G01N27/406 , B82B1/00
CPC classification number: H01L29/775 , B82Y40/00 , G01N27/06 , G01N27/3278 , G01N33/48707 , H01L29/66477
Abstract: PURPOSE: A nano wire sensor having a nano wire of a network structure and a manufacturing method thereof are provided to make an object material react to a detection material in a lateral surface and lower part of a nano wire because the nano wire maintains an original structure without being bent or transformed even the length of a channel is long. CONSTITUTION: A nano wire sensor having a nano wire of a network structure comprises a source electrode(30-1), a drain electrode(30-2), and a probe material(40). The source electrode and drain electrode are formed on the top of a substrate(10). The nano wire is formed in between the source and drain electrodes into a network structure in which patterns of a cross point repeat. The detection material is fixed to the nano wire and selectively reacts with an object material(41) flowing in from outside.
Abstract translation: 目的：提供一种具有网络结构的纳米线及其制造方法的纳米线传感器，以使得物体材料与纳米线的侧表面和下部的检测材料反应，因为纳米线保持原始结构 即使通道的长度长，也不会弯曲或变形。 构成：具有网络结构的纳米线的纳米线传感器包括源电极（30-1），漏电极（30-2）和探针材料（40）。 源电极和漏电极形成在衬底（10）的顶部上。 纳米线形成在源电极和漏电极之间的网络结构中，其中交叉点的图案重复。 检测材料固定在纳米线上，并与从外部流入的物体（41）选择性地反应。
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公开(公告)号：KR1020120048480A
公开(公告)日：2012-05-15
申请号：KR1020110109864
申请日：2011-10-26
Applicant: 포항공과대학교 산학협력단
CPC classification number: H03F1/0288 , H03F1/56 , H03F3/2176 , H03F3/602 , H03F2200/192 , H03F2200/543
Abstract: PURPOSE: A 3-way Doherty power amplifier using a drive amplifier is provided to obtain high efficiency and gain in a wide output power range by preventing gain and efficiency from being reduced. CONSTITUTION: A 3-way Doherty power amplifier(500) includes a hybrid power divider(501), a drive amplifier(502), and a first power splitter(503). The 3-way Doherty power amplifier includes a carrier amplifier(504), a first transmission line(505), and a second power splitter(506). The 3-way Doherty power amplifier includes a first peaking amplifier(507), a second transmission line(508), and a second peaking amplifier(509). The 3-way Doherty power amplifier includes a third transmission line(510), a first λ/4 transmission line(511), and an output impedance conversion transmission line(512).
Abstract translation: 目的：提供使用驱动放大器的3路Doherty功率放大器，通过防止增益和效率降低，在宽输出功率范围内获得高效率和增益。 构成：3路Doherty功率放大器（500）包括混合功率分配器（501），驱动放大器（502）和第一功率分配器（503）。 3路Doherty功率放大器包括载波放大器（504），第一传输线（505）和第二功率分配器（506）。 3路Doherty功率放大器包括第一峰化放大器（507），第二传输线（508）和第二峰化放大器（509）。 3路Doherty功率放大器包括第三传输线（510），第一λ/ 4传输线（511）和输出阻抗转换传输线（512）。
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公开(公告)号：KR1020110085340A
公开(公告)日：2011-07-27
申请号：KR1020100005078
申请日：2010-01-20
Applicant: 포항공과대학교 산학협력단
CPC classification number: H03F3/602 , H03F1/0288 , H03F3/195 , H03F3/211 , H03F3/24 , H03F2200/222 , H03F2200/387 , H03F2200/423 , H03F2200/543 , H03F2203/21106 , H03F2203/21142
Abstract: PURPOSE: A distributed Doherty power amplifier is provided to offset a third distortion signal generated in first and second Doherty power amplifiers, thereby reducing the third distortion signal of the distributed Doherty power amplifier. CONSTITUTION: A signal generating unit(300) comprises a first reference signal generator, a second reference signal generator, and a coupler. A first path unit(301) comprises a first λ/2 transmission line, a first λ/4 transmission line, and a first capacitor. A first Doherty amplifier(303) comprises a first carrier amplifier and a first peaking amplifier. A second Doherty amplifier(305) comprises a second carrier amplifier and a second peaking amplifier. A second path unit(306) comprises a second λ/2 transmission line, a second λ/4 transmission line, and a second capacitor.
Abstract translation: 目的：提供分布式Doherty功率放大器来抵消第一和第二Doherty功率放大器中产生的第三个失真信号，从而减少分布式Doherty功率放大器的第三个失真信号。 构成：信号发生单元（300）包括第一参考信号发生器，第二参考信号发生器和耦合器。 第一路径单元（301）包括第一λ/ 2传输线，第一λ/ 4传输线和第一电容器。 第一Doherty放大器（303）包括第一载波放大器和第一峰值放大器。 第二Doherty放大器（305）包括第二载波放大器和第二峰值放大器。 第二路径单元（306）包括第二λ/ 2传输线，第二λ/ 4传输线和第二电容器。
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