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公开(公告)号：KR1019950011998B1
公开(公告)日：1995-10-13
申请号：KR1019920008887
申请日：1992-05-26
Applicant: 한국전자통신연구원
IPC: H01S5/30
Abstract: The method comprises a step of growing heterostructure, deposited sequentially with a buffer layer, n-type activation layer, and a surface layer, a step of depositing a silicon nitride layer on the epitaxially-grown layer and etching the silicon nitride layer, a step of injecting p-type impurities into the activation doping region and forming a diffusion layer by the first annealing, a step of forming a protective layer on the surface of wafer and forming p-type activation layer by the second annealing, and a step of forming an isolated region by etching the ohmic contact of the protective layer.
Abstract translation: 该方法包括生长异质结构的步骤，依次沉积缓冲层，n型活化层和表面层，在外延生长层上沉积氮化硅层并蚀刻氮化硅层的步骤，步骤 将p型杂质注入激活掺杂区域并通过第一退火形成扩散层，在晶片表面上形成保护层并通过第二退火形成p型活化层的步骤，以及形成步骤 通过蚀刻保护层的欧姆接触来形成隔离区域。
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公开(公告)号：KR1019940010927B1
公开(公告)日：1994-11-19
申请号：KR1019910024511
申请日：1991-12-26
Applicant: 한국전자통신연구원
IPC: H01L29/772 , H01L29/778
Abstract: The method includes the steps of applying a photosenstive film on a GaAs substrate to form a photosenstive film pattern theron to etch the substrate by using a wet etching method, sequentially forming an initial GaAs layer (6), an AlAs layer (7) and an active GaAs layer (8) on the etched substrate by using an MBE process, forming an ohmic contact metal (5) on the epitaxial layers (6,7,8), and selectively etching the Al-As layer (7) by using HCl or buffered oxide etchant (BOE), thereby forming an air gap (9) to isolate the GaAs active layer (8) from the substrate to prevent the current leakage between the buffered film and substrate.
Abstract translation: 该方法包括以下步骤：在GaAs衬底上施加光敏膜以形成光敏膜图案，以通过使用湿蚀刻方法蚀刻衬底，顺序形成初始GaAs层（6），AlAs层（7）和 通过使用MBE工艺在蚀刻的衬底上的有源GaAs层（8），在外延层（6,7,8）上形成欧姆接触金属（5），并且通过使用HCl来选择性地蚀刻Al-As层（7） 或缓冲氧化物蚀刻剂（BOE），从而形成气隙（9）以将GaAs有源层（8）与衬底隔离以防止缓冲膜和衬底之间的电流泄漏。
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公开(公告)号：KR1019940009594B1
公开(公告)日：1994-10-15
申请号：KR1019910016479
申请日：1991-09-20
IPC: H01L21/28
Abstract: The method speeds up the PIN photo diode. An N+-InGaAs (InGaAsP) (22) is formed on a semi-insulation InP board (21), and an n--InGaAs (23) is formed. The p-plate electrode unit (200) pad is formed on the n+-InGaAs (22). The Pn contactor is formed by Zn diffusion. The n-plate electrode unit (100) pad is formed on the SiNx. The p-InP is etched on the surface in order to improve the ohmic contact characteristic. The diffusion of Zn is formed to pn contaction in order to improve the proton effectiveness, and reduce leak current. The diffusion of n+-InGaAs layer supplies the constant voltage to the n-area.
Abstract translation: 该方法加速了PIN光电二极管。 在半绝缘InP板（21）上形成N + -InGaAs（InGaAsP）（22），形成n-InGaAs（23）。 p板电极单元（200）焊盘形成在n + -InGaAs（22）上。 Pn接触器由Zn扩散形成。 n型板电极单元（100）焊盘形成在SiNx上。 在表面上蚀刻p-InP以改善欧姆接触特性。 Zn的扩散形成为pn连接，以提高质子效应，并减少漏电流。 n + -InGaAs层的扩散向n区提供恒定电压。
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Patent Agency Ranking
公开(公告)号：KR1019940004015B1
公开(公告)日：1994-05-10
申请号：KR1019910024516
申请日：1991-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/30
Abstract: The method manufactures an ultra thin film GaAs quantum well with vacuum barriers. The method comprises: A) forming a GaAs buffer layer (2) on a silicon gallium arsenide substance (1); B) alternative depositing aluminum arsenide layers (5) and GaAs layers (4) by MBE method; C) sealing the multiquantum well with silicon nitride (6); D) forming the photoresist pattern using masks (8) after coating photoresist (7); E) removing silicon nitride with HF and etching the GaAS layer and AlAs layer in the area of the photoresist pattern; F) and forming the GaAs vacuum barrier quantum wells by etching the AlAs layers between the GaAs layers.
Abstract translation: 该方法制造具有真空屏障的超薄膜GaAs量子阱。 该方法包括：A）在砷化硅镓物质（1）上形成GaAs缓冲层（2）; B）通过MBE方法替代沉积砷化铝层（5）和GaAs层（4）; C）用氮化硅（6）密封多量子阱; D）在涂覆光致抗蚀剂（7）之后，使用掩模（8）形成光致抗蚀剂图案; E）用HF去除氮化硅并在光致抗蚀剂图案的区域中蚀刻GaAS层和AlAs层; F）并通过蚀刻GaAs层之间的AlAs层来形成GaAs真空势垒量子阱。
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公开(公告)号：KR1019940004014B1
公开(公告)日：1994-05-10
申请号：KR1019910024772
申请日：1991-12-28
Applicant: 한국전자통신연구원
IPC: H01L21/20
Abstract: electrically isolating the elements by mesa-etching the epitaxial growth layer including a cap layer laminated with GaAs layer, AlAs layer and GaAs layer; forming a source and a drain by forming a photoresist pattern and selectively vapor-depositing and heat-treating an ohmic metal layer; forming a depletion gate region by etching GaAs cap layer and an enhancement gate region by etching GaAs cap layer and AlAs cap layer in turn; and forming a depletion gate and enhancement gate by vapor-depositing gate metal on each rigion. The depletion and enhancement gates capable of exactly controlling a threshold voltage is simultaneously formed. Without the depreciation of electrical properties.
Abstract translation: 通过台面蚀刻包括层叠有GaAs层，AlAs层和GaAs层的覆盖层的外延生长层来电隔离元件; 通过形成光致抗蚀剂图案并选择性地气相沉积和热处理欧姆金属层来形成源极和漏极; 通过依次蚀刻GaAs覆盖层和AlAs覆盖层，通过蚀刻GaAs覆盖层和增强栅极区域来形成耗尽栅极区域; 以及通过在每个焊缝上气相沉积栅极金属来形成耗尽栅极和增强栅极。 同时形成能够精确控制阈值电压的耗尽和增强门。 没有电气特性的折旧。
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公开(公告)号：KR1019930015064A
公开(公告)日：1993-07-23
申请号：KR1019910024510
申请日：1991-12-26
Applicant: 한국전자통신연구원
IPC: H01L29/78
Abstract: 본 발명은 갈륨비소 금속반도체 전계효과 트랜지스터를 제조하는 방법에 관한 것으로, 반절연 반도체기판(1)상에 규소박막(105)을 증착하고, 포토리소그라피에 의해 감광막(102a)으로 채널영역을 정의한 후 n형 불순물을 1차 이온주입하고, 고농도 도핑용 n
+ 리소그라피에 의해 감광막(102b)으로 오옴전극 접합영역을 정의한 후 2차 이온주입하고, 상기 감광막(102b)을 제거한 후 보호막(107)을 기판표면 전체에 증착하고 이어 열처리하며, 상기 열처리 공정이 완료된 후 상기 보호막(107)과 상기 규소박막(105)을 차례로 제거하고, 오믹전극용 마스크를 포토리소그라피 하여 감광막으로 오믹전극의 패턴을 형성한후 기판표면을 리세스 에치하여 손상영역을 제거한후 오믹전극(104)을 형성하고 합금화하며, 게이트용 마스크를 사용한 포토리소그라피로 게이트 패턴 형성한후 기판표면을 리세스 에치하여 손상영역을 제거한후 게이트(109)를 형성하는 단계들을 포함한다. -
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