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公开(公告)号：KR101683341B1
公开(公告)日：2016-12-07
申请号：KR1020140105774
申请日：2014-08-14
Applicant: 한양대학교 산학협력단
IPC: H01L31/09 , H01L31/103 , H01L31/18
CPC classification number: Y02P70/521
Abstract: UV 센서및 그제조방법을제공한다. UV 센서는기판, 상기기판상에위치하는제1 전극, 상기제1 전극상에위치하되, 절연체물질을포함하는절연체층, 상기절연체층상에위치하되, 산화물반도체를포함하는산화물반도체층및 상기산화물반도체층상에위치하는제2 전극을포함하고, 상기절연체층과상기산화물반도체층사이에서정류특성을갖고, UV 조사에따른제1 전극및 제2 전극사이의광전류변화를이용한다. 따라서, 산화물반도체와절연체층사이에일어나는정류효과를이용하여, UV 센서의 off-current를낮출수 있다.
Abstract translation: 提供一种紫外线（UV）传感器及其制造方法。 UV传感器包括：基板; 位于所述基板上的第一电极; 绝缘体层，其位于所述第一电极上并且包括绝缘材料; 位于所述绝缘体层上且包含氧化物半导体的氧化物半导体层; 以及位于所述氧化物半导体上的第二电极。 UV传感器在绝缘体层和氧化物半导体层之间具有整流特性，并且使用由UV照射引起的第一和第二电极之间的光电流变化。 因此，本发明可以通过使用在氧化物半导体层和绝缘体层之间产生的整流效应来减少UV传感器的截止电流。
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公开(公告)号：KR1020150126994A
公开(公告)日：2015-11-16
申请号：KR1020150048938
申请日：2015-04-07
Applicant: 한양대학교 산학협력단
IPC: H01L29/66 , H01L21/316 , H01L21/318 , H01L21/28
Abstract: 정류다이오드및 그제조방법을제공한다. 이러한정류다이오드는절연체물질을포함하는절연체층및 상기절연체층상에위치하고, n형 ZnO 계열산화물반도체를포함하는반도체층을포함하고, 상기절연체층과상기반도체층사이에서정류특성을갖는것을특징으로한다. 따라서, 향상된전기적특성을갖는정류다이오드를제공할수 있다. 또한, 기존산화물다이오드와비교하였을때 많은제약을받는 P-type 산화물반도체를절연체층으로대체함에따라, 재료선택의폭이보다넓어질수 있다. 따라서, 전기적특성변화의조절범위또한넓힐수 있다.
Abstract translation: 提供一种整流二极管及其制造方法。 整流二极管包括绝缘体层，其包括绝缘体材料和位于绝缘体层上并且包括n型ZnO基氧化物半导体并且具有在绝缘体层和半导体层之间的整流特性的半导体层。 因此，提供了具有改进的电气特性的整流二极管。 此外，与现有的氧化物二极管相比，通过用绝缘体层替代具有许多限制的P型氧化物半导体来扩展材料的选择。 因此，电气特性变化的控制范围变宽。
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公开(公告)号：KR1020150091900A
公开(公告)日：2015-08-12
申请号：KR1020140012695
申请日：2014-02-04
Applicant: 주식회사 레이언스 , 한양대학교 산학협력단
IPC: H01L27/146
CPC classification number: H01L27/14692 , H01L27/14609
Abstract: 본 발명은 소스전극 및 드레인전극과; 상기 소스전극 및 드레인전극과 접촉하는 산화물반도체층과; 상기 산화물반도체층 상에 형성된 게이트절연막과; 상기 게이트절연막 상에 형성된 게이트전극과; 상기 드레인전극과 연결되는 포토다이오드를 포함하는 이미지센서를 제공한다.
Abstract translation: 本发明提供了一种图像传感器，其包括源电极，漏电极，与源电极和漏极接触的氧化物半导体层，形成在氧化物半导体层上的栅极绝缘层，栅电极 其形成在栅极绝缘层上，以及连接到漏电极的光电二极管。
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公开(公告)号：KR1020150018668A
公开(公告)日：2015-02-24
申请号：KR1020130094024
申请日：2013-08-08
Applicant: 주식회사 레이언스 , 한양대학교 산학협력단
IPC: H01L27/146
CPC classification number: H01L27/14616 , H01L27/14632 , H01L27/14687 , H01L27/14692 , H01L29/78618 , H01L29/78633 , H01L29/7869
Abstract: 본 발명은 게이트전극 상에 형성된 산화물반도체층과; 상기 산화물반도체층의 채널영역의 표면에 형성된 산화막과; 상기 산화물반도체층 상에, 상기 채널영역을 사이에 두고 이격된 소스전극 및 드레인전극과; 상기 소스전극 및 드레인전극 상에, 상기 산화막을 덮는 식각방지막과; 상기 드레인전극과 연결되는 포토다이오드를 포함하는 이미지센서를 제공한다.
Abstract translation: 本发明提供一种用于改善电性能的图像传感器，其包括形成在栅电极上的氧化物半导体层，形成在氧化物半导体层的沟道区域的表面上的氧化物层，源电极和漏极 电极，其通过插入沟道区域分别布置在氧化物半导体层上;蚀刻停止层，形成在源电极和漏电极上以覆盖氧化物层;以及光电二极管，连接到漏电极。
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公开(公告)号：KR101006868B1
公开(公告)日：2011-01-12
申请号：KR1020080116346
申请日：2008-11-21
Applicant: 한양대학교 산학협력단
IPC: H01L27/115 , H01L21/8247 , B82Y10/00
Abstract: 본 발명은 간단한 공정으로 제작이 가능하면서 멀티 비트가 명확히 구현되는 멀티 비트 비휘발성 메모리 소자에 관한 것이다. 본 발명에 따른 멀티 비트 비휘발성 메모리 소자는 기판 상에 터널링 절연층, 전하 트랩층, 컨트롤 절연층 및 게이트 전극이 적층되어 형성된다. 그리고 터널링 절연층 및 컨트롤 절연층 중 적어도 하나의 절연층은 일부분이 나머지 부분과 서로 다른 두께를 갖도록 형성된다.
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Patent Agency Ranking
公开(公告)号：KR1020100120939A
公开(公告)日：2010-11-17
申请号：KR1020090039824
申请日：2009-05-07
Applicant: 국민대학교산학협력단 , 한양대학교 산학협력단
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L21/26
Abstract: PURPOSE: A manufacturing method of a thin film transistor is provided to inexpensively improve the electrical property of a thin film transistor by executing an ultraviolet irradiation process instead of a thermal processing process in an oxide semiconductor active layer. CONSTITUTION: A gate electrode(110) is formed on a substrate(100). A gate insulating layer(120) is formed on the substrate. A semiconductor active layer(130) is formed on the gate insulating layer. An ultraviolet ray is irradiated onto the semiconductor active layer. A source/drain electrode is formed on the semiconductor active layer.
Abstract translation: 目的：提供薄膜晶体管的制造方法，通过在氧化物半导体活性层中执行紫外线照射处理而不是热处理工艺来廉价地提高薄膜晶体管的电性能。 构成：在基板（100）上形成栅电极（110）。 在基板上形成栅极绝缘层（120）。 半导体有源层（130）形成在栅极绝缘层上。 紫外线照射到半导体活性层上。 源极/漏电极形成在半导体有源层上。
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公开(公告)号：KR1020100018131A
公开(公告)日：2010-02-17
申请号：KR1020080076755
申请日：2008-08-06
Applicant: 한양대학교 산학협력단
IPC: H01L29/786
CPC classification number: H01L27/1274 , H01L27/124
Abstract: PURPOSE: A method for crystallizing an amorphous thin film and a wiring structure for performing the same is provided to offer an uniform electric current density flowing in all amorphous thin films arranged in the form of the matrix by improving the wiring structure for the crystallization of the FALC(Field Aided Lateral Crystallization) process. CONSTITUTION: A basic unit(600) can extend from a first unit arranged in the matrix type of 2 x 2 to a n-th unit arranged in the matrix type of 2 n(N is the natural number more than 2). A basic unit comprises a cell(610) including the amorphous thin film arranged in the matrix type of 2 x 2. The basic unit comprises a (+) cell electrode(620) connecting one side of the cell arranged in each heat of 2 of 2 and a (-) cell electrode(630) connecting the other side of the cell arranged in each heat of 2 of 2. Also, the basic unit includes a (+) connecting electrode(640) connecting two (+) cell electrodes and a (-) connecting electrode(650) connecting two (-) cell electrodes.
Abstract translation: 目的：提供一种使非晶薄膜结晶的方法和用于实现该非晶薄膜的布线结构的方法，以提供均匀的电流密度，其通过改进用于晶体结晶的布线结构来提供以矩阵形式布置的所有非晶薄膜中的流动 FALC（场辅助横向结晶）工艺。 构成：基本单元（600）可以从以2×2的矩阵类型布置的第一单元延伸到以矩阵2n排列的第n单元（N为大于2的自然数）。 基本单元包括包括以2×2矩阵形式布置的非晶薄膜的单元（610）。基本单元包括（+）单元电极（620），连接单元电极（620） 2的连接电极（640），连接两个（+）电池电极的（+）连接电极（640）和连接两个（+）电池电极的（+）连接电极 连接两个（ - ）单元电极的（ - ）连接电极（650）。
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公开(公告)号：KR100876396B1
公开(公告)日：2008-12-29
申请号：KR1020070086885
申请日：2007-08-29
Applicant: 한양대학교 산학협력단
IPC: G02F1/136 , H01L29/786
CPC classification number: H01L27/1274 , H01L27/1277 , H01L27/1285
Abstract: A method for crystallizing channel region for poly-Si TFT array substrate fabrication using FALC process is provided to apply poly-Si TFT-LCD, and OLED by regulating crystallization rate of each TFT element. A plurality of thin film transistor elements in which the channel region is made of the amorphous silicon prepares TFT array substrate which is arranged to row and column. A common source electrode spreading along the arrangement direction of row right and left is formed. A common drain electrode which is spread along the parallel to common source electrode direction by connecting one of drain electrode end which are formed each row. A second voltage applying terminal is formed on the right side terminal between the common drain electrodes.
Abstract translation: 提供了使用FALC工艺制造多晶硅TFT阵列基板制造的沟道区域的结晶方法，通过调节每个TFT元件的结晶速率来应用多晶硅TFT-LCD和OLED。 多个薄膜晶体管元件，其中沟道区域由非晶硅制成，准备布置成行和列的TFT阵列基板。 形成沿左右行排列方向扩散的公共源电极。 通过连接形成于各排的漏电极端之一，沿着共同的源电极方向平行扩散的公共漏电极。 第二电压施加端子形成在公共漏电极之间的右侧端子上。
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公开(公告)号：KR1020080022326A
公开(公告)日：2008-03-11
申请号：KR1020060085631
申请日：2006-09-06
Applicant: 한양대학교 산학협력단
Abstract: A method of manufacturing p-type ZnO using pulsed rapid thermal annealing is provided to easily convert an n-type ZnO film into a p-type ZnO film at a low temperature. N-type zinc oxide is deposited on a substrate to form a ZnO film, and then the n-type ZnO film is doped with p-type dopant element. The ZnO film doped with the dopant element is subjected to heat treatment by repeatedly applying heat having a peak temperature between 500 and 1000 deg.C while a base temperature is maintained in a range of 0 to 500 deg.C. The heat treatment is repeatedly performed by applying the base temperature during several seconds to several times and the peak temperature during several seconds to several minutes.
Abstract translation: 提供使用脉冲快速热退火制造p型ZnO的方法，以便在低温下容易地将n型ZnO膜转变成p型ZnO膜。 在基板上沉积N型氧化锌以形成ZnO膜，然后将n型ZnO膜掺杂有p型掺杂元素。 掺杂掺杂剂元素的ZnO膜通过在基础温度保持在0〜500℃的范围内，通过重复施加峰值温度在500〜1000℃之间的热进行热处理。 通过将基础温度施加几秒到几次并且峰值温度在几秒至几分钟内重复进行热处理。
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公开(公告)号：KR100806681B1
公开(公告)日：2008-02-26
申请号：KR1020060085630
申请日：2006-09-06
Applicant: 한양대학교 산학협력단
Abstract: A preparation method of high conductive ZnO by pulsed rapid thermal annealing is provided to prepare ZnO which has high conductivity and can be used on an inexpensive substrate having a low melting point. A preparation method of high conductive ZnO comprises the steps of: forming a ZnO-based thin film on a glass substrate; doping a donor-forming element onto the ZnO-based thin film; and subjecting the ZnO-based thin film to thermal annealing by repeatedly increasing temperature of the substrate to a peak temperature ranging from 500 to 1000 deg.C while maintaining a substrate on which the ZnO-based thin film is formed to a base temperature. The step of forming the ZnO-based thin film and the step of doping the ZnO-based thin film with the donor-forming element are carried out simultaneously. The donor-forming element is a group III element selected from aluminum(Al), gallium(Ga), indium(In) and boron(B) that are group III elements in the periodic table in the elements.
Abstract translation: 提供通过脉冲快速热退火的高导电性ZnO的制备方法，以制备具有高导电性的ZnO并且可以用于具有低熔点的廉价基板上。 高导电ZnO的制备方法包括以下步骤：在玻璃基板上形成ZnO基薄膜; 将供体形成元素掺杂到ZnO基薄膜上; 并且通过将衬底的温度重复地提高至500〜1000℃的峰值温度，同时将ZnO系薄膜进行热退火，同时将其上形成ZnO基薄膜的基板保持在基底温度。 形成ZnO基薄膜的步骤和与供体形成元件掺杂ZnO基薄膜的步骤同时进行。 供体形成元素是选自元素周期表中的III族元素的铝（Al），镓（Ga），铟（In）和硼（B））中的III族元素。
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