公开(公告)号：EP0978141A1

公开(公告)日：2000-02-09

申请号：EP98912999.4

申请日：1998-03-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HAUSE, Frederick, N. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

IPC: H01L21/8238

CPC classification number: H01L21/823814

Abstract: A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.

公开(公告)号：EP0912996A1

公开(公告)日：1999-05-06

申请号：EP97929752.0

申请日：1997-05-27

Applicant: Advanced Micro Devices, Inc.

Inventor： BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21 ,  H01L23

CPC classification number: H01L23/5222 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.

公开(公告)号：EP0943119B1

公开(公告)日：2001-07-11

申请号：EP97952347.9

申请日：1997-12-04

Applicant: Advanced Micro Devices, Inc.

Inventor： MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F7/20

CPC classification number: G03F7/70433 ,  G03F1/70 ,  G03F7/70241

Abstract: A reticle (130) provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions (132, 134) for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.

公开(公告)号：EP1070343A1

公开(公告)日：2001-01-24

申请号：EP98953682.6

申请日：1998-10-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： DAWSON, Robert ,  MAY, Charles, E.

IPC: H01L21/3105 ,  H01L21/321 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L21/31051 ,  H01L21/32115

Abstract: A method is provided for obtaining a topography with a substantially planar upper surface. The profile of the upper surface of the semiconductor topography is first detected by a profile detection tool, such as a stylus profilometer. The profile detection tool creates a database to quantify the elevational variations across the upper surface of the semiconductor topography. The database is then provided to a control system of a deposition tool. The control system controls the deposition of a profile layer upon the upper surface of the semiconductor topography such that a thickness of the profile layer is a function of the elevation of the surface. In one embodiment, the control system controls a potential gradient across the semiconductor topography so as to cause more reactant species to be directed toward the more recessed regions of the topography. In another embodiment, the control system controls the opening and closing of valves disposed within a shower head above the semiconductor topography. More reactant species are allowed to pass from those valves positioned directly above the more recessed regions of the topography. The resulting upper surface of the semiconductor topography is thus planar.

公开(公告)号：EP0978141B1

公开(公告)日：2006-07-12

申请号：EP98912999.4

申请日：1998-03-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： HAUSE, Frederick, N. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

IPC: H01L21/8238

CPC classification number: H01L21/823814

Abstract: A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.

公开(公告)号：EP0963606B1

公开(公告)日：2005-10-26

申请号：EP97907668.4

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： FULFORD, H., Jim, Jr. ,  BANDYOPADHYAY, Basab ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

公开(公告)号：EP0912996B1

公开(公告)日：2002-01-02

申请号：EP97929752.0

申请日：1997-05-27

Applicant: Advanced Micro Devices, Inc.

Inventor： BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.

公开(公告)号：EP1070348B1

公开(公告)日：2014-03-12

申请号：EP98955236.9

申请日：1998-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： DAWSON, Robert ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  FULFORD, H., Jim, Jr. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

IPC: H01L21/768

CPC classification number: H01L21/76895

公开(公告)号：EP1029344A1

公开(公告)日：2000-08-23

申请号：EP98953699.0

申请日：1998-10-16

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHEN, Robert, C. ,  SHIELDS, Jeffrey, A. ,  DAWSON, Robert ,  TRAN, Khanh

IPC: H01L21/314 ,  H01L21/768

CPC classification number: H01L21/314 ,  H01L21/76826 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Spin-on HSQ (52) is employed to gap fill metal layers in manufacturing a high density, multimetal layer semiconductor device. The degradation of deposited HSQ layers during formation of borderless vias (55), as from photoresist stripping using an O2-containing plasma, is overcome by treating the degraded HSQ layer (52) with an H2-containing plasma to restore the dangling Si-H bonds, thereby passivating the surface and preventing moisture absorption, before filling the via opening with conductive material (56, 57), such as a barrier layer (57).

公开(公告)号：EP1010200A1

公开(公告)日：2000-06-21

申请号：EP98923905.8

申请日：1998-06-03

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： GARDNER, Mark, I. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  HAUSE, Frederick, N. ,  KADOSH, Daniel ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

IPC: H01L21/336 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823814 ,  H01L29/1033 ,  H01L29/518 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833

Abstract: A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source. Such a liner is particularly advantageous for boron-doped source/drain regions, and may be combined with N-channel IGFETs formed without such liners.