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    Programmable logic with embedded memory blocks
    21.
    发明专利
    Programmable logic with embedded memory blocks 未知

    公开(公告)号：GB2351824A

    公开(公告)日：2001-01-10

    申请号：GB0016223

    申请日：2000-06-30

    Applicant: ALTERA CORP

    Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

    IPC: G11C5/02 ,  H03K19/177

    Abstract: A high-performance programmable logic architecture has embedded memory arranged at peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703,706) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements can be directly programmable routed and connected to driver blocks of the logic blocks in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources. Using similar direct programmable interconnections the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size

    Embedded memory blocks for programmable logic
    23.
    发明专利
    Embedded memory blocks for programmable logic 未知

    公开(公告)号：GB2391671A

    公开(公告)日：2004-02-11

    申请号：GB0324461

    申请日：2000-06-30

    Applicant: ALTERA CORP

    Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

    IPC: H03K19/177

    Abstract: A high-performance programmable logic architecture has embedded memory arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703,706) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements can be directly programmable routed and connected to driver blocks of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources. Using similar direct programmable interconnections the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources.

    25.
    发明专利
    未知

    公开(公告)号：DE60012639T2

    公开(公告)日：2005-08-04

    申请号：DE60012639

    申请日：2000-03-02

    Applicant: ALTERA CORP

    Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

    IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    26.
    发明专利
    未知

    公开(公告)号：DE60012639D1

    公开(公告)日：2004-09-09

    申请号：DE60012639

    申请日：2000-03-02

    Applicant: ALTERA CORP

    Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

    IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    Programmable receiver equalization circuit and method
    28.
    发明专利
    Programmable receiver equalization circuit and method 有权
    可编程接收器均衡电路和方法

    公开(公告)号：JP2012130047A

    公开(公告)日：2012-07-05

    申请号：JP2012022868

    申请日：2012-02-06

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： MAANGAT SIMARDEEP ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  TU NGOC TRAN

    IPC: H04B3/04 ,  H04L25/02 ,  H04L25/03

    CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04L25/03019

    Abstract: PROBLEM TO BE SOLVED: To provide an equalization circuit for appropriately compensating for attenuation caused by transmission media.SOLUTION: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. An equalization circuit (106) includes a plurality of stages (202) arranged in series to allow frequency responses of the stages (202) to be integrated together. Each stage (202) is programmable to insert a zero, thus causing the frequency response of the stage (202) to be increased in magnitude by 20 dB/decade. The frequency location of zero is also programmable to allow each stage (202) to contribute to a certain amount of a gain for a specific frequency. Each stage (202) is also programmable to determine the location of a pole for the reduction of high frequency noise and cross-talk cancellation.

    Abstract translation: 要解决的问题：提供用于适当地补偿由传输介质引起的衰减的均衡电路。 解决方案：通过传输介质传输的数据信号受到传输介质所造成的衰减。 均衡电路（106）包括串联布置的多个级（202），以允许级（202）的频率响应被集成在一起。 每个级（202）可编程为插入零，从而使得级（202）的频率响应在幅度上增加20dB /十倍。 零的频率位置也是可编程的，以允许每个级（202）为特定频率贡献一定量的增益。 每个级（202）也是可编程的，以确定用于降低高频噪声和串扰消除的极点的位置。 版权所有（C）2012，JPO＆INPIT

    Programmable receiver equalization circuit and method
    29.
    发明专利
    Programmable receiver equalization circuit and method 有权
    可编程接收器均衡电路和方法

    公开(公告)号：JP2007028625A

    公开(公告)日：2007-02-01

    申请号：JP2006193262

    申请日：2006-07-13

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： MAANGAT SIMARDEEP ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  TRAN THUNGOC

    IPC: H04B3/04 ,  H04L25/03

    CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04L25/03019

    Abstract: PROBLEM TO BE SOLVED: To provide an equalization circuit for appropriately compensating for attenuation caused by transmission media.
    SOLUTION: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry (106) may include a plurality of stages (202) arranged in series to allow frequency responses of the stages (202) to be aggregated together. Each stage (202) may be programmable to insert a zero, thus causing the frequency response of the stage (202) to be increased in magnitude by 20 dB/decade. The frequency location of zero may also be programmable to allow each stage (202) to contribute to a certain amount of a gain for a specific frequency. Each stage (202) may also be programmable to determine the location of a pole for the reduction of high frequency noise and cross-talk cancellation.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于适当地补偿由传输介质引起的衰减的均衡电路。 解决方案：通过传输介质传输的数据信号受到传输介质所造成的衰减。 均衡电路（106）可以包括串联布置的多个级（202），以允许级（202）的频率响应聚合在一起。 每个级（202）可以是可编程的以插入零，从而使得级（202）的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级（202）为特定频率贡献一定量的增益。 每个级（202）也可以被编程以确定用于降低高频噪声和串扰消除的极点的位置。 版权所有（C）2007，JPO＆INPIT

    High-speed serial data signal receiver circuitry
    30.
    发明专利
    High-speed serial data signal receiver circuitry 有权
    高速串行数据信号接收电路

    公开(公告)号：JP2009147947A

    公开(公告)日：2009-07-02

    申请号：JP2008320309

    申请日：2008-12-16

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： DING WEIQI ,  LIU MENGCHI ,  WONG WILSON ,  SHUMARAYEV SERGEY

    IPC: H04L25/03 ,  H04B3/04 ,  H04L27/01

    CPC classification number: H04L25/03878 ,  H04L7/0054

    Abstract: PROBLEM TO BE SOLVED: To provide a data conversion process which can convert a serial data format to a parallel data format successfully and efficiently, and also to provide a data conversion process in the opposite direction. SOLUTION: The receiver circuitry for receiving high-speed serial data signals having serial bit rates in the range of about 10 Gbps includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Each of the stages has variable parameters of a DC gain, and a pole and/or zero whose location is variable with respect to frequency. The parameters of the DC gain at each stage and the locations of the pole and/or zero are variable by programs. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供可以成功且有效地将串行数据格式转换为并行数据格式的数据转换处理，并且还提供相反方向的数据转换处理。 解决方案：用于接收具有大约10Gbps范围内的串行比特率的高速串行数据信号的接收机电路包括仅具有两个串联连接级的两级连续时间线性均衡器。 每个级具有DC增益的可变参数，以及位置相对于频率可变的极点和/或零点。 每个阶段的直流增益参数和极点和/或零点的位置都可以通过程序来实现。 版权所有（C）2009，JPO＆INPIT

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