公开(公告)号：WO2016053469A1

公开(公告)日：2016-04-07

申请号：PCT/US2015/043688

申请日：2015-08-04

Applicant: APPLE INC.

Inventor： ZHAI, Jun

IPC: H01L25/16 ,  H01L21/60 ,  H01G4/40 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01G4/40 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/528 ,  H01L24/09 ,  H01L24/14 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L28/10 ,  H01L28/40 ,  H01L2221/68327 ,  H01L2224/0812 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/16268 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor device is described that includes an integrated circuit (500) coupled to a first semiconductor substrate (100) with a first set of passive devices (e.g., inductors) (102) on the first substrate. A second semiconductor substrate (200) with a second set of passive devices (e.g., capacitors) (202) may be coupled to the first substrate. Interconnects (104) in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization (106,502).

Abstract translation: 描述了包括在第一基板上与第一组无源器件（例如，电感器）（102）耦合到第一半导体衬底（100）的集成电路（500）的半导体器件。 具有第二组无源器件（例如，电容器）（202）的第二半导体衬底（200）可以耦合到第一衬底。 衬底中的互连（104）可以允许衬底和集成电路之间的互连。 无源器件可用于为集成电路提供电压调节。 衬底和集成电路可以使用金属化（106,502）耦合。

公开(公告)号：WO2016036544A1

公开(公告)日：2016-03-10

申请号：PCT/US2015/046803

申请日：2015-08-25

Applicant: APPLE INC.

Inventor： HAN, Caleb C. ,  JIANG, Tongbi ,  ZHAI, Jun

IPC: B81B7/00

CPC classification number: G01L7/08 ,  B81B7/0048 ,  B81B2201/025 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/094 ,  B81C1/0023 ,  B81C2203/0792 ,  G01L9/0045 ,  G01L9/0048 ,  G01L19/0618 ,  G01L19/146 ,  G01L19/148 ,  H01L41/094 ,  H01L41/1136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48095 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/1461 ,  H01L2924/16151 ,  H01L2924/16195

Abstract: Sensor packages and manners of formation are described. In an embodiment, a sensor package includes a supporting die characterized by a recess area and a support anchor protruding above the recess area. A sensor die is bonded to the support anchor such that an air gap exists between the sensor die and the recess area. The sensor die includes a sensor positioned directly above the air gap.

Abstract translation: 描述传感器封装和形成方式。 在一个实施例中，传感器封装包括支撑模具，其特征在于凹部区域和在凹部区域上方突出的支撑锚固件。 传感器模具结合到支撑锚定件，使得在传感器模具和凹部区域之间存在气隙。 传感器模具包括位于空气间隙正上方的传感器。

公开(公告)号：WO2013012634A2

公开(公告)日：2013-01-24

申请号：PCT/US2012/046248

申请日：2012-07-11

Applicant: APPLE INC. ,  ZHAI, Jun ,  VON KAENEL, Vincent R.

Inventor： ZHAI, Jun ,  VON KAENEL, Vincent R.

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1713 ,  H01L2224/4824 ,  H01L2224/81815 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15321 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module.

Abstract translation: 具有安装在基板的相对侧上的两个或多个集成电路管芯的半导体器件模块。 集成电路管芯通过使用表面安装连接来安装，例如使用导电凸块实现的倒装芯片连接。 系统可以包括一个或多个当前的半导体器件模块，并且在一些情况下还可以包括其他模块，诸如系统模块。

公开(公告)号：WO2023049597A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/075471

申请日：2022-08-25

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  YEH, Jung-Cheng ,  HU, Kunzhong ,  CAMENFORTE, Raymundo ,  HOFFMANN, Thomas

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L23/66

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：WO2021201990A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/017445

申请日：2021-02-10

Applicant: APPLE INC.

Inventor： CHEN, Wei ,  ZHAO, Jie-Hua ,  ZHAI, Jun ,  CHANG, Po-Hao ,  LIN, Hsien-Che ,  KE, Ying-Chieh ,  HU, Kunzhong

IPC: H01L23/04 ,  H01L23/16 ,  H01L23/367 ,  H01L25/065 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L23/24 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L2924/15311 ,  H01L2924/1615 ,  H01L2924/16151 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

公开(公告)号：WO2020112505A3

公开(公告)日：2020-06-04

申请号：PCT/US2019/062702

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  LAI, Kwan-Yu ,  HU, Kunzhong ,  RAMACHANDRAN, Vidhya

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/60 ,  H01L23/29

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure (310) to connect a die set (110, 110) embedded in an inorganic gap fill material (130).

公开(公告)号：WO2020112505A2

公开(公告)日：2020-06-04

申请号：PCT/US2019/062702

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  LAI, Kwan-Yu ,  HU, Kunzhong ,  RAMACHANDRAN, Vidhya

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/60

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：WO2018226394A2

公开(公告)日：2018-12-13

申请号：PCT/US2018/033813

申请日：2018-05-22

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  ZHONG, Chonghua ,  HU, Kunzhong

Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

公开(公告)号：WO2016164119A1

公开(公告)日：2016-10-13

申请号：PCT/US2016/020289

申请日：2016-03-01

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  ZHONG, Chonghua ,  PANG, Mengzhi ,  YANG, Se Young

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83

Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) (130) formed directly on a top die (110), and a bottom die (150) mounted on a back surface of the RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装包括直接形成在顶模（110）上的再分配层（RDL）（130）和安装在RDL的后表面上的底模（150）。

公开(公告)号：WO2016140819A2

公开(公告)日：2016-09-09

申请号：PCT/US2016/018804

申请日：2016-02-19

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  LAI, Kwan-Yu ,  PANG, Mengzhi ,  ZHONG, Chonghua ,  YANG, Se Young

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08167 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/27 ,  H01L2924/014

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL）以及附接到第一RDL的前侧和后侧的多个管芯。 第一和第二RDL与从第一RDL的后侧延伸到第二RDL的前侧的多个导电柱连接在一起。