METHOD FOR MANUFACTURING SLANT SIDEWALL TO APERTURE OF MASK MATERIAL LAYER

    公开(公告)号:JP2002231718A

    公开(公告)日:2002-08-16

    申请号:JP2001378598

    申请日:2001-12-12

    Applicant: FORMFACTOR INC

    Abstract: PROBLEM TO BE SOLVED: To form a hyperfine small-sized spring contact element on a semiconductor device. SOLUTION: A mask layer 220 is formed on the surface of a substrate 202 like an electronic component. An aperture is formed on the mask layer. Conductive trace of a seed layer 250 is deposited on the mask layer and in the aperture, and a block of conductive material is constituted on the trace. Consequently, a hyperfine electronic contact structure 260 is defined lithographically and manufactured. The side wall of the aperture is tapered. The conductive trace can be patterned by depositing material via a stencil or a shadow mask. A protruding fixture 230 can be so arranged on the mask layer that a tip 264 of the contact structure obtains topology. All of the constituents are constituted as a group, and a plurality of elastic contact structure bodies which are positioned precisely can be formed.

    Test method and assembly including test die for testing semiconductor product die
    26.
    发明专利
    Test method and assembly including test die for testing semiconductor product die 审中-公开
    测试方法和组装,包括用于测试半导体产品的测试仪

    公开(公告)号:JP2010249824A

    公开(公告)日:2010-11-04

    申请号:JP2010106806

    申请日:2010-05-06

    Abstract: PROBLEM TO BE SOLVED: To provide a test assembly (2000) for testing product circuitry (202, 302, 304) of a product die (2011, 300). SOLUTION: The test assembly includes a test die (2010, 400) and an interconnection substrate (2008) for electrically coupling the test die to a host controller (2002). The test die may be designed, in accordance with a design methodology (100) for a test die and a product die that includes the step of concurrently designing test circuitry (202A, 402, 404) and product circuitry in a unified design (102). The test circuitry can be designed, to provide a high degree of fault detection range for the corresponding product circuitry generally, substantially without relating to the amount of silicon region that is required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die (104). The test die includes the test circuitry, and the product die includes the product circuitry. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题:提供用于测试产品模具(2011,300)的产品电路(202,302,304)的测试组件(2000)。 解决方案:测试组件包括用于将测试模具电耦合到主机控制器(2002)的测试模具(2010,400)和互连衬底(2008)。 可以根据用于测试模具的设计方法(100)和产品模具来设计测试模具,该产品模具包括在统一设计(102)中同时设计测试电路(202A,402,404)和产品电路的步骤, 。 可以设计测试电路,以基本上不对与测试电路所要求的硅区域量有关,为相应的产品电路提供高度的故障检测范围。 然后,设计方法将统一设计分为测试模具和产品模具(104)。 测试芯片包括测试电路,产品芯片包括产品电路。 版权所有(C)2011,JPO&INPIT

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