公开(公告)号：GB2447795B

公开(公告)日：2009-03-18

申请号：GB0807135

申请日：2005-06-07

Applicant: HRL LAB LLC

Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

Abstract: An apparatus and method for preventing information leakage attacks through a polarized cryptographic bus architecture. The polarized cryptographic bus architecture randomly changes the polarity of the target bit such that the leaked information cannot be consistently averaged to yield statistical key material. Further, to increase the prevention of information leakage attacks, a set of dual rails is used to write data to a given register bit.

公开(公告)号：GB2447804A

公开(公告)日：2008-09-24

申请号：GB0810628

申请日：2005-06-07

Applicant: HRL LAB LLC

Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: G06F21/00 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/02 ,  H04L9/00 ,  H04L9/06

Abstract: The invention prevents information leakage attacks that utilise timeline alignment such as Differential Power Analysis (DPA). Data processing in a CPU is concealed by inserting a random number of instruction fetch cycles during execution of a program and, while the random number of instruction fetch cycles is occurring, mimicking the power consumption associated with fetching instructions from memory, executing the instructions in program sequence, and writing results to memory registers. The mimicking of power consumption is achieved by fetching and executing instructions but inhibiting the updating of normal memory locations, for example by updating a dummy memory location instead. At the conclusion of the random number of instructions, normal program execution recommences by re-fetching the same instructions which were initially fetched but this time updating memory locations in the normal way. The insertion of the random number of instruction fetch cycles may be controlled by a Random Instruction Mask (RIM) control flag. Other embodiments are disclosed, including a cryptographic bus architecture that prevents usage of side channel information by randomly toggling the polarity of a target bit at a data bus driver.

公开(公告)号：GB2432971A

公开(公告)日：2007-06-06

申请号：GB0702704

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: The similarity of non-operable and operable transistors in an integrated circuit is increased by ensuring that the distance between the gate and source or drain electrodes is the same for both types of transistor. The use of non-operable transistors allow the circuit designer to disguise an AND gate so that it appears to be an OR gate to the reverse engineer. The disguised non-operable transistors cause the circuitry to operate in an unexpected manner to the reverse engineer.

公开(公告)号：GB2422956B

公开(公告)日：2007-05-23

申请号：GB0608053

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

公开(公告)号：GB2430515A

公开(公告)日：2007-03-28

申请号：GB0623489

申请日：2005-06-07

Applicant: HRL LAB LLC

Inventor： SHU DAVID B ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: G06F21/02 ,  G06F1/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F21/00 ,  H04L9/00 ,  H04L9/06

Abstract: An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.

公开(公告)号：GB2391986B

公开(公告)日：2005-08-10

申请号：GB0325521

申请日：2002-03-12

Applicant: HRL LAB LLC

Inventor： CLARK JR WILLIAM M ,  CHOW LAP-WAI ,  BAUKUS JAMES P

IPC: G11C17/18 ,  G06F12/14 ,  G11C7/12 ,  G11C7/18 ,  G11C7/24 ,  G11C16/02 ,  G11C16/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/10 ,  H01L27/112 ,  H01L27/115

Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.

公开(公告)号：GB2405531A

公开(公告)日：2005-03-02

申请号：GB0427115

申请日：2003-05-06

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  BAUKUS JAMES P

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/115 ,  H01L29/732 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.

公开(公告)号：AU2003293540A1

公开(公告)日：2004-07-09

申请号：AU2003293540

申请日：2003-12-10

Applicant: HRL LAB LLC

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P ,  HARBISON GAVIN J

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/76

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

公开(公告)号：DE10196819T5

公开(公告)日：2004-04-15

申请号：DE10196819

申请日：2001-05-11

Applicant: HRL LAB LLC

Inventor： CLARK JUN WILLIAM M ,  BAUKUS JAMES P ,  CHOW LAP-WAI

IPC: H01L27/04 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/768

公开(公告)号：AU2003245265A1

公开(公告)日：2003-12-02

申请号：AU2003245265

申请日：2003-05-06

Applicant: HRL LAB LLC

Inventor： CLARK JR WILLIAM M ,  BAUKUS JAMES P ,  CHOW LAP-WAI

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/115 ,  H01L29/732 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792