-
公开(公告)号：DE69817159D1
公开(公告)日：2003-09-18
申请号：DE69817159
申请日：1998-05-29
Applicant: IBM
Inventor： BLANC ALAIN , BREZZO BERNARD , SAUREL ALAIN
IPC: H04L12/54 , H04L49/111 , H04L12/56
Abstract: A Switching system (15 or 25) receiving data cells from a set of n input ports and to be routed to one or more output ports in accordance with the contents of a bitmap value introduced in the cell at the entrance of said module, said module comprising a shared buffer for storing the cells which are to be routed. The systems further comprises a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process for either transporting the considered cell to the output port or discarding the latter. Two switching systems are combined in a first and a second Switch Fabrics (10, 20) in order to respectively form a first and second switch cores, located in a centralized building and a set of Switch Core Access Layer (S.C.A.L.) elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of one of said switching system. A set of Port Adapters (30; 31) are distributed at different physical areas and are connected to said first and second Switch Fabrics via a particular SCAL element so that each Switching system (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch cores. The mask achieves the distribution of the first and second switching systems between the different attached Port adapters, thus providing a load balancing between the two switching systems permitting to associate their individual buffering resources.
-
公开(公告)号：DE69809224T2
公开(公告)日：2003-08-28
申请号：DE69809224
申请日：1998-08-28
Applicant: IBM
Inventor： BLANC ALAIN , ORENGO GERARD , PORET MICHEL
Abstract: A switching apparatus comprising a centralized Switch Core (10) and at least one SCAL element for the attachment of Protocol Adapters. The Switch Core and the SCAL communicate to each other via n parallel serial links with each one transmitting a Logical Unit. Each SCAL comprises both the receive and the transmit part at least one input for receiving cells from said Protocol Adapter; a set of n FIFO queues (21-25) for storing the cells into n parallel busses; and a set of n RAM storages, with each RAM being associated with one Logical Unit. First multiplexing means (31) receive the contents of the parallel busses for performing simultaneously n WRITE operations into the n RAM storages under control of a first set of n tables ( 36-39). Second multiplexing (41) means are provided for making READ operations from said n RAM storages under control of a second set of n tables ( 46-49). By appropriate arrangement of the two sets of tables, which are chosen complementary, the cells which are conveyed through the first multiplexing means, the RAMs and the second multiplexing means are subject to a cell rearrangement enabling to introduce at least one bitmap field, thereby producing said four Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage (50-80), one particular byte is accidentally stored into one RAM available for a Write operation by means of said first set of tables, thereby causing an alteration to the normal association between said n RAMs and said n Logical Units which is then restablished by said second set of tables.
-
公开(公告)号：DE69223508T2
公开(公告)日：1998-06-25
申请号：DE69223508
申请日：1992-07-10
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , RICHTER GERARD
-
公开(公告)号：DE69125816T2
公开(公告)日：1997-10-23
申请号：DE69125816
申请日：1991-02-21
Applicant: IBM
Inventor： BLANC ALAIN , GOHL-ROUX SYLVIE , UNGERBOECK GOTTFRIED
Abstract: DCE and method for performing the processing of data into a DCE, and DCE which includes a digital signal processor DSP (202) for processing the data transmitted between a Data terminating equipment DTE (209) and a telecommunication line, transmit (213) and receive (214) circuits being connected to the DTE interface. The DCE further includes A/D (215) and a D/A converters (216) for respectively converting the data from an analog form to Pulse Coded Modulation PCM words and from PCM words to an analog form and also a control processor (200) for controlling the communication protocols and a storage (204) which is connected to both the DSP processor (202) and the control processor (200). The method is characterized in that it involves the steps of storing (403) by means of said DSP processor (202) the bits provided by said transmit circuit (213) into a first queue (300) which is located into said storage (204) and storing (507) into a second queue (304) which is also located into the same storage (204) the characters being computed by said DSP processor (202) and deriving from the bits stored into said first queue (300) accordingly to a first given transmission protocol being either a start-stop, a HDLC or a BSC transmission protocol. The method further involves the step of storing (513) into a third queue (307) which is located into the same storage as above the characters being provided by said control processor (200) in order to be transmitted to a remote DCE via the telecommunication line. A further step is involved which is the storing (513) into a fourth queue (309) which is still located into the storage (204) the bits being computed by said DSP processor (202) and deriving from the characters stored into said third queue (307) accordingly to a second given transmission protocol. the transmission of data through the telecommunication line is achieved by storing into a fifth queue (302) the PCM words which are computed by said DSP processor (202) in accordance with a given modulation algorithm, the PCM words being derived either from the contents of said first (300) queue in synchronous mode or from the contents of the third (307) queue when the transmit part of the DCE is intended to operate in an asynchronous mode or still when the control processor (200) wishes to transmit data through the telecommunication line. The selection of an appropriate transmission protocol, chosen the existing protocols such as start-stop, HDLC, BSC, as well as the selection of the appropriate modulation algorithm provides a method for processing data to be transmitted from a DTE to a telecommunication line which allows a large number of configuration without requiring the great number of electronic components which were usually necessary. The invention also provides the receive part of the DCE.
-
公开(公告)号：DE3783915T2
公开(公告)日：1993-08-19
申请号：DE3783915
申请日：1987-10-19
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , LALLEMAND ERIC
Abstract: Predictive clock extracting circuit which having means for determining the duration between two consecutive transitions of a multilevel digital signal, and means for generating a pulse SPL at half the said duration after a the transition following on two consecutive previous transitions. A phase locked oscillator (23) driven by said SPL pulse generates the extracted clock signal, in phase with pulse SPL and which coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N (20) which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs, the result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. A divide by 2 circuit (21) divides the result N(i) stored into the first counter at second transition. The preferred embodiment of the invention also involves an an up/down counter which generates a second counter K that is expected to be representative of half the value of the first counter N(i). This second counter K is used to generate the extracted clock in phase with the middle of the eye intervals. Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor. A comparator comparing K(i) and N(i)/2 controls the update of the current value K(i) according the following rules. if the value K(i) is superior to N(i)/2 at the second transition, then the counter K is updated by decrementing its current value. Conversely, when N(i) is inferior to N(i)/2, then counter K is updated by incrementing its current value. In this way, the extracted clock which will be derived from counter K varies slowly and integrates sudden variations of the content of the first counter N. A counter P (22) initialized with the updated value K(i+1) of counter K starts running from K(i+1) to zero in response to the detection of the transition following on two said first and second transition and delivers a pulse SPL whenever its content reaches the value zero. The phase locked oscillator (23) controlled by the pulse SPL generates the extracted clock which is likely to coincide with the middle of the eye pattern.
-
Patent Agency Ranking26.发明专利
公开(公告)号：CA2060976A1
公开(公告)日：1992-08-22
申请号：CA2060976
申请日：1992-02-11
Applicant: IBM
Inventor： BLANC ALAIN , GOHL-ROUX SYLVIE , UNGERBOECK GOTTFRIED
Abstract: DCE and method for performing the processing of data into a DCE, and DCE which includes a digital signal processor DSP (202) for processing the data transmitted between a Data terminating equipment DTE (209) and a telecommunication line, transmit (213) and receive (214) circuits being connected to the DTE interface. The DCE further includes A/D (215) and a D/A converters (216) for respectively converting the data from an analog form to Pulse Coded Modulation PCM words and from PCM words to an analog form and also a control processor (200) for controlling the communication protocols and a storage (204) which is connected to both the DSP processor (202) and the control processor (200). The method is characterized in that it involves the steps of storing (403) by means of said DSP processor (202) the bits provided by said transmit circuit (213) into a first queue (300) which is located into said storage (204) and storing (507) into a second queue (304) which is also located into the same storage (204) the characters being computed by said DSP processor (202) and deriving from the bits stored into said first queue (300) accordingly to a first given transmission protocol being either a start-stop, a HDLC or a BSC transmission protocol. The method further involves the step of storing (513) into a third queue (307) which is located into the same storage as above the characters being provided by said control processor (200) in order to be transmitted to a remote DCE via the telecommunication line. A further step is involved which is the storing (513) into a fourth queue (309) which is still located into the storage (204) the bits being computed by said DSP processor (202) and deriving from the characters stored into said third queue (307) accordingly to a second given transmission protocol. the transmission of data through the telecommunication line is achieved by storing into a fifth queue (302) the PCM words which are computed by said DSP processor (202) in accordance with a given modulation algorithm, the PCM words being derived either from the contents of said first (300) queue in synchronous mode or from the contents of the third (307) queue when the transmit part of the DCE is intended to operate in an asynchronous mode or still when the control processor (200) wishes to transmit data through the telecommunication line. The selection of an appropriate transmission protocol, chosen the existing protocols such as start-stop, HDLC, BSC, as well as the selection of the appropriate modulation algorithm provides a method for processing data to be transmitted from a DTE to a telecommunication line which allows a large number of configuration without requiring the great number of electronic components which were usually necessary. The invention also provides the receive part of the DCE.
-
公开(公告)号：DE69737676D1
公开(公告)日：2007-06-14
申请号：DE69737676
申请日：1997-08-19
Applicant: IBM
Inventor： BLANC ALAIN , SAUREL ALAIN , BREZZO BERNARD , PORET MICHEL
IPC: H04L49/111 , H04Q11/04
Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.
-
公开(公告)号：DE69734968T2
公开(公告)日：2006-07-27
申请号：DE69734968
申请日：1997-08-19
Applicant: IBM
Inventor： BLANC ALAIN , NICOLAS LAURENT , GOHL SYLVIE
IPC: H04L12/54 , H04L49/111 , H04Q11/04
Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit includes means for introducing at least one extra byte to every cell. The extra byte is reserved for carrying a routing header for controlling the switching structure in a first step, and then for use by the PINT circuit when the cell will be received by the transmit part in a second step. The transmit part of each PINT circuit comprises a control module that receives all the cells generated at the corresponding output port and controls whether to discard the cell based on the value of the extra byte.
-
公开(公告)号：DE69819129T2
公开(公告)日：2004-07-29
申请号：DE69819129
申请日：1998-10-29
Applicant: IBM
Inventor： BLANC ALAIN , BREZZO BERNARD , DEBORD PIERRE , WIDMER ALBERT
Abstract: A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested. When the incoming flow provides data cells, the invention uses a predetermined bit within the data cell, generally that immediately following the beginning of the cell, in order to carry the flow control information.
-
公开(公告)号：DE69819129D1
公开(公告)日：2003-11-27
申请号：DE69819129
申请日：1998-10-29
Applicant: IBM
Inventor： BLANC ALAIN , BREZZO BERNARD , DEBORD PIERRE , WIDMER ALBERT
Abstract: A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested. When the incoming flow provides data cells, the invention uses a predetermined bit within the data cell, generally that immediately following the beginning of the cell, in order to carry the flow control information.
-
-
-
-
-
-
-
-
-
Search Results
43
records
(took 0.02 seconds)
