公开(公告)号：GB2371381B

公开(公告)日：2004-09-01

申请号：GB0108545

申请日：2001-04-05

Applicant: IBM

Inventor： BASS BRIAN M ,  CALVIGNAC JEAN L ,  HEDDES MARCO C ,  MARAGKOS ANTONIOS ,  SIEGEL MICHAEL S ,  VERPLANKEN FABRICE J ,  PATEL PIYUSH ,  JEFFRIES CLARK D ,  RINALDI MARK A

IPC: G06F17/30 ,  H04L12/701 ,  H04L12/741 ,  H04L12/743

Abstract: A method of performing a search based upon a search criterion using a tree is proposed. In use an input is read as a search key and the most significant bits are used as an index to a search table representing a plurality of search nodes. Each non empty entry in the search table will contain a pointer to the next branch of the tree. The search table may use a hash function to generate an index key. A determination is then made if the pointer points to a leaf or branch of the tree. If the pointer is to a branch the procedure is repeated until a leaf object is identified and returned to the calling application. In no entry is found that matches the search a no match is returned. The search criterion may be a longest prefix match in which instance the method is executed to find the position of the distinguishing bit.

公开(公告)号：GB2371381A

公开(公告)日：2002-07-24

申请号：GB0108545

申请日：2001-04-05

Applicant: IBM

Inventor： BASS BRIAN M ,  CALVIGNAC JEAN L ,  HEDDES MARCO C ,  MARAGKOS ANTONIOS ,  SIEGEL MICHAEL S ,  VERPLANKEN FABRICE J ,  PATEL PIYUSH ,  JEFFRIES CLARK D ,  RINALDI MARK A

IPC: G06F17/30 ,  H04L12/701 ,  H04L12/741 ,  H04L12/743

Abstract: A method of performing a search based upon a search criterion using a tree is proposed. In use an input is read as a search key and the most significant bits are used as an index to a search table representing a plurality of search nodes. Each non empty entry in the search table will contain a pointer to the next branch of the tree. The search table may use a hash function to generate an index key. A determination is then made if the pointer points to a leaf or branch of the tree. If the pointer is to a branch the procedure is repeated until a leaf object is identified and returned to the calling application. In no entry is found that matches the search a no match is returned. The search criterion may be a longest prefix match in which instance the method is executed to find the position of the distinguishing bit.

公开(公告)号：DE10110504A1

公开(公告)日：2001-10-18

申请号：DE10110504

申请日：2001-03-03

Applicant: IBM

Inventor： DAVIS GORDON TAYLOR ,  HEDDES MARCO C ,  LEAVENS ROSS BOYD ,  VERPLANKEN FRABRICE JEAN

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F15/16

Abstract: The method involves providing several instruction execution threads as independent processes in a sequential time frame. The execution threads are arranged in a queue so that they have overlapping access to the accessible data. A first thread in the queue is executed, and the execution control is transferred to the next thread in the queue when an event occurs that blocks the execution of the first thread. Independent claims are included for a processing system, a method of executing several independent threads in a processor, the use of a prefetch buffers in connection with a number of independent instruction threads, and for a thread execution controller.

公开(公告)号：ES2265971T3

公开(公告)日：2007-03-01

申请号：ES00959158

申请日：2000-08-24

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO C ,  RAO SRIDHAR ,  SIEGEL MICHAEL STEVEN

IPC: G06F13/00 ,  G06F15/16 ,  G06F13/38 ,  G06F13/40 ,  G06F15/00 ,  G06F15/173 ,  G06F15/177 ,  G06F15/76 ,  H04L12/56

Abstract: Aparato que comprende: un procesador del punto de control; un dispositivo de interfaz conectado operativamente a dicho procesador del punto de control por un camino de control y que proporciona un camino de datos de alta velocidad, teniendo dicho dispositivo de interfaz un substrato (10) de semiconductores; una pluralidad de procesadores (12) del interfaz formados sobre dicho substrato, siendo el número de dichos procesadores al menos cinco; una memoria interna de instrucciones formada sobre dicho substrato y que almacena instrucciones de manera accesible para dichos procesadores del interfaz; una memoria interna de datos formada sobre dicho substrato y que almacena datos que pasan a través de dicho dispositivo, de manera accesible para dichos procesadores del interfaz; y una pluralidad de puertos de entrada/salida formados sobre dicho substrato; conectando al menos uno de dichos puertos de entrada/salida a dicha memoria interna de datos con la memoria externa de datos; intercambiando, al menos otros dos de dichos puertos de entrada/salida, datos que pasan a través del dispositivo de interfaz, con una red externa a la velocidad del medio bajo la dirección de dichos procesadores del interfaz; cooperando dicho procesador del punto de control con dicho dispositivo de interfaz, cargando en el interior de dicha memoria de instrucciones las instrucciones que han de ser ejecutadas por dichos procesadores del interfaz al dirigir el intercambio de datos entre dichos puertos de entrada/salida de intercambio de datos y el flujo de datos a través de dicha memoria de datos.

公开(公告)号：HK1069046A1

公开(公告)日：2005-05-06

申请号：HK05102297

申请日：2005-03-15

Applicant: IBM

Inventor： ALLEN JAMES JR ,  BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  GAUR SANTOSH PRASAD ,  HEDDES MARCO C ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F15/16 ,  G06F15/177 ,  H04L20060101 ,  H04J20060101 ,  H04L12/56 ,  H04Q20060101 ,  H04Q3/00 ,  H04Q3/545

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

公开(公告)号：GB2366426B

公开(公告)日：2004-11-17

申请号：GB0108828

申请日：2001-04-09

Applicant: IBM

Inventor： DAVIS GORDON TAYLOR ,  HEDDES MARCO C ,  LEAVENS ROSS BOYD ,  RINALDI MARK A

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/16 ,  G06F15/17

Abstract: A network processor utilizes protocol processor units (PPUs) to provide instruction communication for the network. Each PPU includes a core language processor (CLP). Each CLP contains general purpose registers and includes a coprocessor that contains scalar registers and array registers. The CLP controls and instructs a plurality of coprocessors that run in parallel with the CLP. Each coprocessor is a specialized hardware assist engine having direct access to the CLP registers and arrays through two sets of interface signals, a coprocessor execution interface and a coprocessor data interface.

公开(公告)号：AU2002251004A1

公开(公告)日：2002-09-19

申请号：AU2002251004

申请日：2002-01-31

Applicant: IBM

Inventor： HANDLOGTEN GLEN HOWARD ,  CALVIGNAC JEAN LOUIS ,  LOGAN JOSEPH FRANKLIN ,  VERPLANKEN FABRICE ,  GOETZINGER WILLIAM JOHN ,  MIKOS JAMES FRANCIS ,  NORGAARD DAVID ALAN ,  HEDDES MARCO C

IPC: H04L12/56 ,  H04L12/44 ,  H04Q11/04

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.

公开(公告)号：CA2328268A1

公开(公告)日：2001-07-04

申请号：CA2328268

申请日：2000-12-12

Applicant: IBM

Inventor： VERPLANKEN FABRICE JEAN ,  TROMBLEY MICHAEL RAYMOND ,  SIEGEL MICHAEL STEVEN ,  HEDDES MARCO C ,  CALVIGNAC JEAN LOUIS ,  BASS BRIAN MITCHELL

IPC: G06F12/00 ,  G06F5/06 ,  G06F5/14 ,  G06F12/02 ,  G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/38

Abstract: A bandwidth conserving queue manager for a FIFO buffer is provided, preferab ly on an ASIC chip and preferably including separate DRAM storage that maintains a FI FO queue which can extend beyond the data storage space of the FIFO buffer to provide additiona l data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multipl e queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffe r storage space in the FIFO buffers is exceeded, data are written to and read from the addition al data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a wa y that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

公开(公告)号：AU1403800A

公开(公告)日：2000-08-01

申请号：AU1403800

申请日：1999-12-10

Applicant: IBM

Inventor： HEDDES MARCO C

IPC: H04L49/111 ,  H04L12/56

Abstract: A switching arrangement comprising a switching device for transporting incoming packets of data containing a data destination part and a data content part, from a plurality of input ports to a plurality of output ports is proposed. The switching device comprises input means for transporting the data content parts of the incoming packets to storing means which contains a plurality of storage packets. It further comprises output means for reading out the stored data content parts and delivering them to a selection of the output ports, which is determined by the data destination part. Additionally the switching device comprises for at least one of the output ports buffering means which is arranged after the output port.