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公开(公告)号：GB1279792A
公开(公告)日：1972-06-28
申请号：GB92871
申请日：1971-01-08
Applicant: IBM
Inventor： HSIAO MU-YUE
IPC: H03M13/19
Abstract: 1279792 Error correction systems INTERNATIONAL BUSINESS MACHINES CORP 8 Jan 1971 [3 Feb 1970] 928/71 Heading G4A An encoder adds r check bits to k data bits, each check bit representing a number of data bits, the average number of data bits per check bit being >(r/2) and not more than r-1, any two check bits representing no more than one common data bit, and each data bit being represented by exactly two check bits (see Fig. 4), and a decoder has input circuitry which supplies to an error correcting circuit for each data bit, the data bit itself and the two combinations of check bits and other data bits representing that data bit, the error-correcting circuit being capable of correcting each data bit as necessary provided no more than one of the inputs for that bit is in error. The check bits may be produced by exclusive OR gates, the decoder may have a pair of exclusive OR gates for each data bit having inputs comprising the corresponding two combinations of check bits and other data bits, and the error-correcting circuit may comprise majority logic circuits receiving inputs from the respective data bits and the corresponding pair of exclusive ORgates, Fig. 6 (not shown). By adding a parity bit c7 for all the data bits, detection of a double error is also made possible. Error syndrome bits, e.g. S1 = c 1 #(m 1 #m 2 #m 3 #m 4 #+m 5 ) are each equal to zero when there is no error in the data and check bits, and the additional syndrome bit S 7 ensures that a single bit error will occur in three syndrome bits. An OR circuit, Fig. 7 (not shown), detects when any S 1 to S 7 = 1 and the inverted output of an adder is 1 for no errors and two errors, so that by gating these two signals together an output indicative of the presence of two errors is obtained.
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公开(公告)号：DE3380573D1
公开(公告)日：1989-10-19
申请号：DE3380573
申请日：1983-03-10
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , HSIAO MU-YUE
Abstract: Swapping of physical bits between different logical words of a memory (40) is accomplished by reference to data (46) on bad bits in the memory. Different permutation data (34) are selected to control address inputs to each bit position (12i) in a memory word so that any word with multiple uncorrectable data is changed to a correctable logical data word by placing one or more of the bad bits in the original word into another word of the memory. The swapping is done by an exclusionary process (48) which identifies and deselects certain deleterious potential combinations of actual addresses thereby limiting the selection process to ohter combinations. The process can involve categorizing (44) of failures in accordance with type, and performing (48) algorithm operations which identify combinations of bit addresses that would result in combining the failures so that there are more errors in any memory word than would be correctable by the error correction code monitoring (42) the memory.
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公开(公告)号：CA1014665A
公开(公告)日：1977-07-26
申请号：CA198452
申请日：1974-04-24
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , HONG SE J , HSIAO MU-YUE , PATEL ARVIND M
Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.
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公开(公告)号：DE2532149A1
公开(公告)日：1976-03-04
申请号：DE2532149
申请日：1975-07-18
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HSIAO MU-YUE , PATEL ARVIND MOTIBHAI
Abstract: This specification describes an error correction system for a high density memory made up of a number of monolithic wafers each containing a plurality of arrays that are addressed thru circuitry and wiring contained on that wafer. The storage bits on the wafers are functionally divided into a number of blocks each containing a plurality of words. The words of each block are on several wafers with each word made up of a plurality of arrays on a single array wafer. Each word in a block is protected by a similar error correction double multiple error detection code. The block is further protected by two additional check words made up using a b-adjacent code. Each byte in the check words protects one byte position of the words of the block. When a single error is detected in any word by the SEC-MED code the code corrects the error. If a multiple error is detected, the multiple error signal points to the word in error to be corrected by the b-adjacent code check words.
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公开(公告)号：DE2425823A1
公开(公告)日：1975-01-02
申请号：DE2425823
申请日：1974-05-28
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HONG SE JUNE , HSIAO MU-YUE , PATEL ARVIND MOTIBHAI
Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.
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Patent Agency Ranking
公开(公告)号：DE2421112A1
公开(公告)日：1975-01-02
申请号：DE2421112
申请日：1974-05-02
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HSIAO MU-YUE , PATEL ARVIND MOTIBHAI
Abstract: 1440285 Error correction INTERNATIONAL BUSINESS MACHINES CORP 24 April 1974 [4 June 1973] 18002/74 Heading G4A Data is stored on a plurality of independently accessible storage units, e.g. magnetic tape cartridges, and check bits, each of which is a function of a corresponding bit from each data storage unit, are stored on a check unit which may be used, in the event of a catastrophic loss of data on one of the data storage units and detected by an error checking facility associated with that unit, to restore the data on that unit. Extension of the system to include more than one check unit, each of which stores the check bits for one position of a Hamming code, is also mentioned. In normal operation, one of the data storage units is selected and data thereon is updated by read before write heads 15, 21. The difference e jk between each old bit and the corresponding new bit is EXORed with the corresponding old parity bit p k from the check unit to update the parity bits. The parity bits are initially recorded by successively (or simultaneously) reading the data storage units to record the modulo 2 sums of the corresponding bits, and data restoration is similar reading from the good data storage units and the check unit.
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公开(公告)号：CA780571A
公开(公告)日：1968-03-12
申请号：CA780571D
Applicant: IBM
Inventor： HSIAO MU-YUE , SIH KWANG YUE
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公开(公告)号：DE69127416D1
公开(公告)日：1997-10-02
申请号：DE69127416
申请日：1991-06-21
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , HSIAO MU-YUE , MULLIGAN JAMES MICHAEL
Abstract: A single width bidirectional bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear measurements, an important consideration in semiconductor manufacturing wherein space on chips and wafers is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
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公开(公告)号：FR2325105A1
公开(公告)日：1977-04-15
申请号：FR7413430
申请日：1974-04-10
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , HONG SE JUNE , HSIAO MU-YUE , PATEL ARVIND M
Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.
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公开(公告)号：CA1002663A
公开(公告)日：1976-12-28
申请号：CA184628
申请日：1973-10-30
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , HAUGH CONNOR F , HSIAO MU-YUE
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