公开(公告)号：DE112010004612T5

公开(公告)日：2013-01-24

申请号：DE112010004612

申请日：2010-09-30

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  BOTULA ALAN B ,  JOSEPH ALVIN J ,  SLINKMAN JAMES A

IPC: H01L27/12

Abstract: Es wird eine Halbleiterstruktur (100) mit einer Isolatorschicht (120) auf einem Halbleitersubstrat (110) und einer Nutzschicht (130) auf der Isolatorschicht beschrieben. Das Substrat (110) ist mit einer relativ geringen Dosis eines Dotanden (111) eines bestimmten Leitungstyps dotiert, sodass es einen relativ hohen spezifischen Widerstand aufweist. Außerdem kann ein der Isolatorschicht unmittelbar benachbarter Teil (102) des Halbleitersubstrats mit einer geringfügig höheren Dosis desselben Dotanden (111), eines verschiedenen Dotanden (112) desselben Leitungstyps oder deren Kombination (111 und 112) dotiert werden. Wahlweise werden innerhalb desselben Teils (102) Mikrokavitäten (122, 123) erzeugt, um eine Erhöhung der Leitfähigkeit durch eine entsprechende Erhöhung des spezifischen Widerstands zu kompensieren. Durch die Erhöhung der Dotandenkonzentration an der Grenzfläche Halbleitersubstrat/Isolatorschicht steigt die Schwellenspannung (Vt) von entstehenden parasitären Kapazitäten an, wodurch das Oberschwingungsverhalten verringert wird. Ferner werden hierin auch Ausführungsformen eines Verfahrens und einer Entwurfsstruktur für eine solche Halbleiterstruktur beschrieben.

公开(公告)号：GB2487860A

公开(公告)日：2012-08-08

申请号：GB201206521

申请日：2010-09-30

Applicant: IBM

Inventor： BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN ,  JOSEPH ALVIN ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

IPC: H01L27/12

Abstract: Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

公开(公告)号：CA2780263A1

公开(公告)日：2011-06-03

申请号：CA2780263

申请日：2010-09-30

Applicant: IBM

Inventor： BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN J ,  JOSEPH ALVIN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

IPC: H01L27/12

Abstract: Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

公开(公告)号：DE69807621D1

公开(公告)日：2002-10-10

申请号：DE69807621

申请日：1998-06-26

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

公开(公告)号：DE69802607D1

公开(公告)日：2002-01-10

申请号：DE69802607

申请日：1998-03-12

Applicant: SIEMENS AG ,  IBM

Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762

公开(公告)号：SG50866A1

公开(公告)日：1998-07-20

申请号：SG1997002420

申请日：1997-07-09

Applicant: IBM ,  SIEMENS AG

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/78 ,  H01L27/105

Abstract: An FET isolated on either side by a trench. The FET has a dielectric layer in the isolating trench along at least one side. The dielectric layer which may be an ONO layer has an oxidation catalyst diffused into it. The oxidation catalyst may be potassium. Gate oxide along the side of the FET in close proximity to the ONO layer is thicker than gate oxide between both sides.