公开(公告)号：CA1005931A

公开(公告)日：1977-02-22

申请号：CA194532

申请日：1974-03-08

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/73 ,  H01L21/00 ,  H01L21/316 ,  H01L21/331 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8222 ,  H01L23/535 ,  H01L27/04 ,  H01L27/12

公开(公告)号：DE2626193A1

公开(公告)日：1976-12-30

申请号：DE2626193

申请日：1976-06-11

Applicant: IBM

Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN

IPC: H01L29/78 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/73 ,  H01L21/72

Abstract: A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BVceo) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.

公开(公告)号：FR2308203A1

公开(公告)日：1976-11-12

申请号：FR7605923

申请日：1976-02-25

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN ,  NESTORK WILLIAM J

IPC: H01L27/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L23/535

Abstract: A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide.

公开(公告)号：DE2612667A1

公开(公告)日：1976-10-28

申请号：DE2612667

申请日：1976-03-25

Applicant: IBM

Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN ,  NESTORK WILLIAM JOHN

IPC: H01L27/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L23/535

Abstract: A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide.

公开(公告)号：CA996280A

公开(公告)日：1976-08-31

申请号：CA185033

申请日：1973-11-05

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L21/822 ,  G01R31/28 ,  H01L21/66 ,  H01L21/82 ,  H01L23/544 ,  H01L27/04

公开(公告)号：DE2521435A1

公开(公告)日：1976-01-15

申请号：DE2521435

申请日：1975-05-14

Applicant: IBM

Inventor： MAGDO STEVEN

IPC: H01L31/10 ,  H01L27/144 ,  H01L27/146 ,  H01L31/00 ,  H01L31/06

Abstract: 1501962 Photosensitive semi - conductor devices INTERNATIONAL BUSINESS MACHINES CORP 5 May 1975 [24 June 1974] 18673/75 Heading H1K A space-charge-limited phototransistor structure comprises lateral emitter, base and collector regions 8, 6, 5 at the surface of a semi-conductor substrate 2 of resistivity at least 10,000 ohm-cm. beneath which, along line B, a space-charge limited current flows between the emitter and collector when the surface base area receives incident radiant energy. More electron-hole separation occurs in region B than in the base region 6, the depth of the base region being less than the reciprocal of the absorption coefficient of the radiant energy. In the integrated circuit shown, adjacent transistors are isolated by a region of opposite type to that of the substrate reverse biased with respect to the collector regions. The base region is at floating potential and when the base surface is illuminated, the collector, which is reverse biased, collects electrons from the pairs generated in both the P base and lower N regions. The remaining holes tend to forward-bias the emitter-base junctions along lines A and B to initiate phototransistor action. Metal shields (40) (Fig. 4, not shown) may be placed over the isolation region and the effective base area may be increased, whilst maintaining the required base width, by extending the collectorbase junction along certain portions only (Figs. 2, 3, not shown). An array of such phototransistors (Fig. 5, not shown) may be used in a document reading scanner.

公开(公告)号：DE3176828D1

公开(公告)日：1988-09-01

申请号：DE3176828

申请日：1981-01-08

Applicant: IBM

Inventor： BARBOUR DONALD ROSS ,  LEMKE GUIDO ALBERT ,  MAGDO STEVEN

IPC: H05K3/46 ,  H01L23/14 ,  H01L23/538 ,  H01L23/66 ,  H01L23/54 ,  H01L23/56

公开(公告)号：DE3371440D1

公开(公告)日：1987-06-11

申请号：DE3371440

申请日：1983-11-03

Applicant: IBM

Inventor： MAGDO STEVEN ,  SATYA AKELLA VENKATA SURYA

IPC: H01L21/66 ,  H01L21/82 ,  H01L23/544

公开(公告)号：CA1143862A

公开(公告)日：1983-03-29

申请号：CA365431

申请日：1980-11-25

Applicant: IBM

Inventor： BARBOUR DONALD R ,  LEMKE GUIDO A ,  MAGDO STEVEN

IPC: H05K3/46 ,  H01L23/14 ,  H01L23/538 ,  H01L23/66 ,  H05K1/14

Abstract: High Performance Semiconductor Package Assembly An improved high performance semiconductor package assembly for interconnecting a plurality of integrated circuit devices having a multilayer substrate with internal wiring including signal wiring and external signal and power connections, a plurality of integrated circuit semiconductor devices supported on the top surface of the substrate in electrically connected operative relation, the improvement being a power supply distribution system for providing electrical supply voltages to the devices from the power connections consisting of radial waveguide structure including parallel waveguide planes with a low input impedence to reduce switching noise, the waveguide planes located between the signal fan-out wiring and internal wiring metallurgy and connected in common to all of the plurality of devices.

公开(公告)号：CA1026469A

公开(公告)日：1978-02-14

申请号：CA223173

申请日：1975-03-21

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H05K3/46 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L

Abstract: An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularitiies at the various levels of the structure are minimized, is produced by a method wherein a first plurality of levels of metallization patterns respectively separated by layers of dielectric material are first formed on a planar primary layer supported on a temporary substrate having a chemical etchability different from that of the layer. The primary layer is electrically insulative with respect to said metallization patterns. Then, a supporting layer is formed on the uppermost covering layer, after which the substrate is removed with a chemical etchant which preferentially etches the substrate away from the insulative layer. Next, an opposite plurality of levels of metallization patterns are formed on the side of the insulative layer opposite to the first formed metallization patterns. These opposite metallization patterns are also respectively separated by covering layers of dielectric material.