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29 records (took 0.021 seconds)

    21.
    发明专利
    未知

    公开(公告)号：DE2262053A1

    公开(公告)日：1973-07-05

    申请号：DE2262053

    申请日：1972-12-19

    Applicant: IBM

    Inventor： MALAVIYA SHASHI DHAR

    IPC: G01R31/26

    Abstract: A first sinusoidal signal at a microwave frequency is applied to the input port of a transistor while simultaneously therewith a second sinusoidal signal at the same frequency is applied to the output port. The magnitude and phase of the signals are adjusted to effect successively short-circuit and open-circuit conditions at the input and output ports. For each condition the magnitudes and phases of the incident and reflected waves are measured or determined at the ports. These measurements may then be used to compute four of the usual transistor parameters and to check the self-consistency of the measurement. A second set of measurements may then be made at a different microwave frequency to compute additional transistor parameters. The beta of the transistor may be directly measured at either microwave frequency.

    22.
    发明专利
    未知

    公开(公告)号：DE69208415D1

    公开(公告)日：1996-03-28

    申请号：DE69208415

    申请日：1992-09-11

    Applicant: IBM

    Inventor： BHATIA HARSARAN SINGH ,  INTERRANTE MARIO JOHN ,  KADAKIA SURESH DAMONDARDAS ,  STOLLER HERBERT IVAN ,  MALAVIYA SHASHI DHAR ,  MCLEOD MARK HARRISON ,  RAY SUDIPTA KUMAR

    IPC: H01L23/12 ,  H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

    Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

    25.
    发明专利
    未知

    公开(公告)号：DE3783672D1

    公开(公告)日：1993-03-04

    申请号：DE3783672

    申请日：1987-05-12

    Applicant: IBM

    Inventor： BHATIA HARSARAN SINGH ,  JONES HARRY JORDAN ,  MALAVIYA SHASHI DHAR

    IPC: H03K19/082 ,  H03K19/086 ,  H03K19/173 ,  H02H3/38 ,  G05F1/20

    Abstract: A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs (46,48), while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors (12,22), the collector dotting of their respective reference transistors (55,56), the emitter dotting of one input transistor (12) and a reference transistor (55) to a constant current source (90), the emitter dotting of the other input transistor (22) and the other reference transistor (56) to a different constant current source (100), and an inhibit circuit (72) for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.

    MEMORY ARRAY
    26.
    发明专利
    MEMORY ARRAY 未知

    公开(公告)号：DE3279997D1

    公开(公告)日：1989-11-23

    申请号：DE3279997

    申请日：1982-07-06

    Applicant: IBM

    Inventor： MALAVIYA SHASHI DHAR

    IPC: G11C11/41 ,  G11C11/34 ,  G11C11/401 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L27/102 ,  H01L29/78

    Abstract: An electronic data storage or memory array having DC stable memory cells which utilize the principle of a unique substrate biasing mechanism, whereby a channel region defined by resistive substrate material and formed under a controlled electrode (20) becomes "pinched off' and, in the process, so affects the DC potential at that electrode as to maintain the pinched off condition. Consequently, the memory cell becomes established in a first DC stable state ("one" state). The principle is preferably embodied in a field effect transistor (22), the resistive channel region being connected in a DC conductive path to a fixed resistor (R1) and a potential source (+V). Accordingly, when appropriate signal levels representing a binary "one" are applied to word and bit lines (WL1, BL1) connected to a first controlling, or gate, electrode and to a second controlling electrode, respectively, of the FET, the described pinch-off occurs, with concomitantly high resistance (R2) in the DC path, such that the potential adjacent the controlled electrode (20) is maintained in the "one" state that was initiated by the signals on the word and bit lines. On the other hand, when signals representing a "zero" are applied to the same controlling electrodes, the resistive channel region (R2) under the controlled electrode (20) is no longer pinched-off, whereby the memory cell becomes established in the second or "zero" DC stable state. Means for reading the stored data in the cell are integrated with the cell.

    29.
    发明专利
    未知

    公开(公告)号：DE2448533A1

    公开(公告)日：1975-05-15

    申请号：DE2448533

    申请日：1974-10-11

    Applicant: IBM

    Inventor： MALAVIYA SHASHI DHAR

    IPC: H03D3/02 ,  H03D13/00 ,  G01R25/00

    Abstract: A phase discriminator, for operation in a phase-locked loop, which is characterized by a virtually infinite capture range. The discriminator comprises circuit means responsive to the input data and clock pulses for generating a signal having a duration indicative of the phase difference between the pulses, a flip-flop which identifies the phase relationship between the pulses, and a current switch circuit responsive to the flip-flop output for generating an output pulse having a potential level indicative of the phase relationship between the input pulses, and responsive to the circuit means for generating the output pulse for a duration proportional to the phase difference between them. The circuit is also capable of locking pulses of widely different frequencies and tolerates a large variation of input pulse widths.

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