公开(公告)号：DE3380837D1

公开(公告)日：1989-12-14

申请号：DE3380837

申请日：1983-05-19

Applicant: IBM

Inventor： LECHATON JOHN S ,  MALAVIYA SASHI DHAR ,  SCHEPIS DOMINIC JOSEPH ,  SRINIVASAN GURUMAKONDA RAMASAM

IPC: H01L27/00 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/306

Abstract: @ A fully isolated dielectric structure for isolating regions (14) of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation (18) with pairs of parallel, anisotropic etched trenches (20) which are subsequently oxidized and filled to give complete dielectric isolation for regions (14) of monocrystalline silicon. The anisotropic etching preferably etches a buried N + sublayer (12) under the monocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches (20).

公开(公告)号：DE3467472D1

公开(公告)日：1987-12-17

申请号：DE3467472

申请日：1984-08-08

Applicant: IBM

Inventor： LECHATON JOHN S ,  PITNER PHILIP MICHAEL ,  SRINIVASAN GURUMAKONDA RAMASAM

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L21/00 ,  H01L29/72

Abstract: A high performance NPN bipolar transistor functioning in a current switch logic circuit is formed within an isolated region of a monocrystalline silicon body (10) wherein the transistor includes an N+ subcollector (12), an N+ collector reach-through (20) which connects the subcollector to a major surface of the silicon body, a P base region (22) above the subcollector and adjacent to the reach-through region, an N+ emitter region (30) within the base region and extending from the major surface. The base region (22) includes intrinsic base region located below the emitter region (30) and an extrinsic region (34) located extending from the major surface and adjacent to the emitter region. The extrinsic base preferably completely surrounds or rings the emitter region. Using a mask (32) with openings (24) only in the areas of the extrinsic base regions a P+ type region (34) is formed by ion implanting with a P type dopant to a depth of less than the depth of the N emitter region (30) followed by a short thermal anneal to activate the P dopant. By the independent control of the intrinsic and extrinsic base resistances the performance of bipolar transistor integrated circuits for current switch logic applications is substantially increased.

公开(公告)号：DE69228792T2

公开(公告)日：1999-10-07

申请号：DE69228792

申请日：1992-11-19

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  NIJHUIS ROLF HENK ,  SRINIVASAN GURUMAKONDA RAMASAM ,  MURLEY PHILIP CLYDE ,  ROBBINS GORDON JAY ,  WALTERS TIMOTHY LAWTON

IPC: H01L23/522 ,  H01L21/60 ,  H01L21/768 ,  H01L23/49 ,  H01L23/556

公开(公告)号：DE69228792D1

公开(公告)日：1999-05-06

申请号：DE69228792

申请日：1992-11-19

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  NIJHUIS ROLF HENK ,  SRINIVASAN GURUMAKONDA RAMASAM ,  MURLEY PHILIP CLYDE ,  ROBBINS GORDON JAY ,  WALTERS TIMOTHY LAWTON

IPC: H01L23/522 ,  H01L21/60 ,  H01L21/768 ,  H01L23/49 ,  H01L23/556

公开(公告)号：DE3468782D1

公开(公告)日：1988-02-18

申请号：DE3468782

申请日：1984-08-08

Applicant: IBM

Inventor： MALAVIYA SHASHI DHAR ,  SRINIVASAN GURUMAKONDA RAMASAM

IPC: H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L21/762 ,  H01L29/732 ,  H01L21/76 ,  H01L21/205